A plurality of lands are arranged in rows. The lands in adjacent rows are disposed in a staggered arrangement. A first interconnecting line is pulled out from each of the lands. Each of the lands is wider than the first interconnecting line in the row direction. A plurality of electrical connection sections are arranged in rows. The electrical connection sections in adjacent rows are disposed in a staggered arrangement. The lands are electrically connected with the electrical connection sections so as to overlap. Each of the electrical connection sections is a part of a second interconnecting line, and an insulating layer is formed between the second interconnecting lineing pattern other than the electrical connection sections and the first interconnecting lineing pattern.
Provided is an electronic component including a pad provided on an active surface of a rectangular chip substrate, a resin protrusion provided along sides of the chip substrate, and a conductive portion which is electrically connected to the pad and which is formed out of a conductive film covering the surface of the resin protrusion. The resin protrusion includes a protruded body extending linearly and a plurality of the resin protrusions are provided on at least one side of the chip substrate to form a clearance in an intermediate portion of the side.
