An internal power supply circuit for a semiconductor integrated circuit includes two constant voltage generators having identical circuit topologies but generating two different constant voltages from an external power supply voltage. The lower constant voltage is selected when the external power supply voltage is below a predetermined level, the higher constant voltage is selected when the external power supply voltage is above the predetermined level, and an internal power supply voltage is generated from the selected constant voltage. The internal power supply voltage is stable over a wide flat region, but can also be raised to a higher level for stress testing of the semiconductor integrated circuit, and the higher level is also stable.

The present invention employs a memory cell structure in that one end of a variable resistance element (1) for storing information by change of electric resistance is connected to a source of a selection transistor (2) to form a memory cell (3) and, in a memory cell array (4), a drain of the selection transistor (2) is connected to a common bit line (BL) in a column direction, the other end of the variable resistance element (1) is connected to a source line (SL) and a gate of the selection transistor (2) is connected to a common word line (WL) in a row direction. In the memory cell structure, an operation of resetting data stored in the memory cell (3) is carried out for each of sectors including the plural memory cells (3) commonly connected to the source line (SL).

A word line voltage generator that generates a word line voltage, which is selectively changed depending on a temperature, a flash memory device including the word line voltage generator, and a method of generating the word line voltage. The word line voltage generator includes a read voltage generator and a controller. The read voltage generator generates a read voltage or a verify voltage based on one of reference voltages in response to an enable control signal and supplies the read voltage or the verify voltage to one of a plurality of global word lines in response to a row decoding signal, during a read operation or a read operation for program verification, of the flash memory device. The controller generates one of the reference voltages in response to a read control signal or a verify control signal. When a temperature is varied, the read voltage generator changes the level of the read voltage or the verify voltage in reverse proportion to the temperature.

An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.

System for a non-volatile memory system is provided. The non-volatile memory system includes a voltage generator system operating in one of a plurality of modes for generating a voltage applied to a memory cell of the non-volatile memory system. For one of the plurality of modes, a first input value is selected for controlling a temperature dependent component of the voltage and a second input value is selected for controlling a temperature independent component of the voltage. The temperature dependent component of the voltage and the temperature independent component of the voltage are controlled independently in response to the first input value and the second input value.