 |
Description  |
|
|
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor circuit device, and particularly to a semiconductor circuit device assembled into a plurality of types of packages. More particularly, the present invention relates to the configuration of a
semiconductor memory device with a common chip configuration allowing assembly into a plurality of types of packages.
2. Description of the Background Art
A semiconductor circuit formed on a semiconductor chip is assembled into a package before shipment as a final product. The semiconductor circuit is electrically connected to on-board wires through a pin terminal of the package, or the package
protects the semiconductor chip against external contamination sources and external destructive factors such as external mechanical stress and external electromagnetism.
Various types of packages are prepared according to the configuration of applicable board systems. Recently, a package referred to as "surface mount device (SMD)" has been widely employed so as to mount semiconductor circuits on both sides of a
board.
FIG. 72 is a schematic diagram showing the appearance of a TSOP (thin small outline package) which is one of conventional SMDs. In FIG. 72, TSOP has an internal semiconductor chip sealed with a mold resin MRJ. Mold resin MRJ is of a rectangular
shape and has terminals PT arranged along both sides thereof. FIG. 72 representatively shows lead terminals arranged along one side of mold resin MRJ.
Each lead terminal PT is normally of a gull-wing lead (an L lead) shape and is soldered on a board. Since lead terminal PT is not inserted into a through hole formed in the board, TSOP can be arranged on each surface of the board.
TSOP is on the order of 1 mm in thickness and is extremely thin. In addition, lead terminal PT is of a gull-wing shape, and therefore, superior in workability as compared with an SOJ (small outline with J leads) package having pin terminals PT
of J lead shape, and a lead pitch can be made smaller.
As such a thin rectangular package having lead terminals PT arranged only along the long side thereof, there are also known, beside TSOP, an SVP (surface vertical package) which is a vertical surface mount device and a USOP (ultra small outline
package) which is as thin as 0.5 mm. These packages are widely employed for assembling semiconductor memory devices.
In applications such as portable equipment, high density mounting is required. In such applications, an MCP (multi chip package) having a plurality of chips arranged therein is employed, instead of an SCP (single chip package), such as TSOP,
having one chip arranged therein. As MCP, there are known an MCM (multi chip module) type MCP having a plurality of chips assembled in an interposer (substrate) two-dimensionally and a stacked type MCP having a plurality of semiconductor chips stacked
on an interposer.
FIG. 73 is a schematic diagram showing the configuration of conventional stacked type MCP. In FIG. 73, stacked type MCP, semiconductor chips CH3 to CH1 are stacked on an interposer IPS. A supporting insulator ISD1 is arranged between
semiconductor chips CH1 and CH2. A supporting insulator ISD2 is arranged between semiconductor chips CH2 and CH3. A supporting insulator ISD3 is arranged between interposer IPS and semiconductor chip CH3.
Through holes are formed in supporting insulator ISD3 and pads formed on semiconductor chip CH3 are connected through solder balls SLS to pads PD formed on interposer IPS.
As for semiconductor chip CH1, solder balls (micro bumps) SLS formed on the pads are electrically connected to pads PD formed on interposer IPS through bonding wires BW1a and BW1b.
Similarly, as to semiconductor chip CH2, solder balls SLS formed on the pads are electrically connected to pads, not shown, formed on interposer IPS through bonding wires BW2a and BW2b. Wiring is made in interposer IPS and pads PD formed on
interposer IPS are connected to bump balls BPS formed on the rear surface of IPS. Internal interconnecting wires may be formed in a supporting insulator ISD.
Semiconductor chips CH1 to CH3 and pads PD are sealed by mold resin MRJ.
As shown in FIG. 73, since stack type MCP has a plurality of semiconductor chips CH1 to CH3 stacked and assembled therein, it is possible to mount a plurality of chips with a small occupation area.
FIG. 74 is a schematic diagram showing the rear surface of MCP. On the rear surface of MCP, bump balls BPS are arranged in an array. These bump balls BPS are connected to solder balls formed on a mounting board. Therefore, MCP employs bump
balls BPS, rather than lead terminals, so as to electrically connect semiconductor chips CH1 to CH3 to an external device. By arranging bump balls BPS in an array form on the rear surface of mold resin MRJ, a large number of bump balls can be arranged
and the number of input and output signals/data can be increased. This package having bump balls arranged in an array form is referred to as "BGP (ball grid package)". MCP is, therefore, a family member of BGP.
A semiconductor memory device is now considered as one example of the semiconductor circuit device. In the semiconductor memory device, a word configuration is changed by setting a bonding pad potential by mask interconnection or bonding wire
connection, so as to cover different word configurations with the same chip configuration. The internal configuration is the same, but only the number of data input/output circuits to be used is different. Thus, it is possible to cover a plurality of
types of word configurations with chip configuration of a kind, improving manufacturing/design efficiency.
However, pad arrangement is different for different package. It is, therefore, necessary to optimize the layout of the internal circuitry of a semiconductor chip individually according to each package. Conventionally, the arrangement of pads is
optimized differently for BGP (ball grid package) and TSOP of SCP, for example.
In the semiconductor memory device, in particular, unlike an embedded DRAM (dynamic random access memory) which is integrated on a semiconductor chip together with a logic circuit, the number of input/output data bits is small (32 bits) and TSOP
is normally employed as an assembling package. In case of the semiconductor memory device, an LOC (lead on chip) structure is conventionally, normally used for such TSOP. In LOC structure, pads are arranged in the central portion of a chip to decrease
a chip area.
In BGP, such an LOC structure is not employed, but wire bonding, TAB (tape automated bonding) and flip chip bonding and other (s) are employed for making electrical connections between chip pads and package terminals (bump balls).
Therefore, semiconductor memory chips having a pad arrangement optimized for such a TSOP package cannot be applied to BGP.
Furthermore, depending on a processing purpose, the storage capacity required for a memory differs. For example, one memory chip of 128 M bits is required for an application of a simple processing, while a memory of the storage capacity of 256 M
bits is required for an application of processing image and audio data in portable equipment.
To implement a memory of 256 M bits using existing memory chips each having a storage capacity of 128 M bits, it is sufficient to employ two memories each of 128 M bits, simply. In this case, if the required storage capacity is to be satisfied
using two TSOPs, the area of memory chips disadvantageously increases to obstruct down-sizing of the portable equipment.
Possible consideration to avoid such obstruction is such that memory chips with the same configuration as those for TSOP are applied to MCP to implement a memory of 256 M bits. However, since MCP is of BGP, the memory chips suited for TSOP
cannot be applied to MCP.
Moreover, a specification required for a memory of 128 M bits differs from that required for a memory of 256 M bits in some cases. For instance, as to a memory of 256 M bits, if a word structure is of 16 bits, an 8K refresh cycle is set. In
contrast, for a memory of 128 M bits with a word structure of 16 bits, the refresh cycle is set to a 4K refresh cycle. Therefore, it is impossible to implement a memory of 256 M bits by simply using two memory chips each having a storage capacity of 128
M bits.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor circuit device applicable to both a single chip package and a multi chip package with the same chip configuration.
It is another object of the present invention to provide a semiconductor memory device having a chip layout capable of forming a multi chip package, using two memory chips each assembled in a single chip package.
It is still another object of the present invention to provide the internal data bus structure of a semiconductor memory device capable of being assembled in a plurality of types of packages.
It is yet another object of the present invention to provide a semiconductor memory device allowing accurate testing of memory cells even in different internal data bus structures, irrespectively of a word structure.
A semiconductor circuit device according to a first aspect of the present invention includes: an internal circuit including memory cells storing data and formed on a semiconductor chip; and a plurality of pads arranged on the periphery of the
chip in a region external to the internal circuit. The plurality of pads include a plurality of data pads arranged being distributed over outer peripheral portions of at least four divided regions of the chip and selectively used in each of the divided
regions in accordance with a word structure of data inputted and outputted by the internal circuit.
A semiconductor circuit device according to a second aspect of the present invention includes: a plurality of memory cells; test write data lines for transferring data written simultaneously into a predetermined number of memory cells among the
plurality of memory cells in a test operation mode; a write circuit for simultaneously writing the data of the test write data lines to the predetermined number of memory cells in the test operation mode; and a compression circuit compressing read data
from the predetermined number of memory cells and outputting a signal indicating a compression result to a test read data line different from the test write data lines. Each of the test write data lines and test read data line transfers both the write
data and the read data in a normal operation mode.
A semiconductor circuit device according to a third aspect of the present invention includes: a plurality of memory cells each requiring refreshing of storage data; a refresh circuit for refreshing the storage data of the plurality of memory
cells in a set refresh cycle; and a refresh cycle setting circuit fixedly setting the refresh cycle in accordance with a package housing the semiconductor circuit device therein.
A semiconductor circuit device according to a fourth aspect of the present invention includes: a plurality of input/output circuits, arranged in four divided regions of a chip, respectively, each inputting and outputting data; and mask pads
arranged corresponding to the respective four divided regions, and inputting a plurality of mask signals for masking data write and read of the input/output circuits in corresponding regions when activated.
A semiconductor circuit device according to a fifth aspect of the present invention includes: a memory array including a plurality of memory cells; a plurality of global data lines each transmitting and receiving data to and from a selected
memory cell of the memory array; a plurality of preamplifier circuits, arranged corresponding to the respective global data lines, each amplifying and outputting the data of a corresponding global data line when activated; an internal data bus having a
predetermined bit width, for transferring output signals of the plurality of preamplifier circuits; a plurality of pads the same in number as and arranged corresponding to the bus lines of the internal data bus; and a pad connection circuit for setting
coupling between the bus lines of the internal data bus and the plurality of pads at least in accordance with word structure information.
By arranging the data pads distributedly in the outer peripheral portions of the four divided regions of the semiconductor chip, it is possible to easily arrange the data pads corresponding to the ball grid array of the multi chip package even if
the semiconductor chip is assembled in a multi chip package, and to utilize the semiconductor chip the same in configuration for the single chip package and for the multi chip package.
By separating the 1-bit test write data transfer bus line from the data line for transferring a multi-bit test read result in a multi-bit test, it is possible to distribute the circuits connected to the bus for writing and reading the test data,
to mitigate bus load, and to transfer the data at high speed in a normal operation mode (since it is unnecessary to connect write/read data buses dedicated to the respective word structures to the same data bus line).
By changing the refresh cycle according to the type of the assembling package, it is possible to execute a refreshing operation in an optimum cycle in accordance with the storage capacity of the memory assembled in the package, ensuring retention
of the storage data.
By applying data input/output mask signals to the memory circuits arranged corresponding to the respective four divided regions of the chip, it is possible to individually mask the data input/output in the respective four divided regions, to
facilitate the connection between the data input/output mask pads and the data terminals, and to simplify the layout of wiring of data lines between the pads and terminals when the semiconductor memory chip is assembled in a multi chip package.
By setting the connection between the internal data bus lines and the pads at least in accordance with word structure information, it is possible to make the configuration of the internal read circuit such as a preamplifier common irrespectively
of the word structure, simplifying the layout of the internal data read section.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram showing the configuration of a semiconductor circuit device assembled in a multi chip package in the first embodiment according to the present invention;
FIG. 2 is a schematic diagram showing the configuration of a main portion of the semiconductor circuit device in the first embodiment according to the present invention;
FIG. 3 is a schematic diagram showing the configuration of a memory array shown in FIG. 2;
FIG. 4 is a schematic diagram showing the configuration of a refresh control circuit and a row related control circuit shown in FIG. 2;
FIG. 5 is a schematic diagram showing the configuration of a bank control circuit shown in FIG. 4 and a row related circuit shown in FIG. 2;
FIG. 6 shows an example of the configuration of a refresh region designation circuit shown in FIG. 4;
FIG. 7A shows refresh target banks in an 8K refresh cycle, and FIG. 7B shows refresh target banks in a 4K refresh cycle;
FIG. 8 shows an example of the configuration of a refresh cycle setting circuit shown in FIG. 2;
FIG. 9 shows another example of the configuration of the refresh cycle setting circuit shown in FIG. 2;
FIG. 10 shows an example of the configuration of a refresh timer shown in FIG. 4;
FIG. 11 shows an example of the configuration of a bias setting circuit shown in FIG. 10;
FIG. 12 shows an example of the configuration of a ring oscillation circuit shown in FIG. 10;
FIG. 13 is a schematic diagram showing another example of the configuration of the refresh timer shown in FIG. 4;
FIG. 14 shows an example of the configuration of a counter shown in FIG. 13;
FIG. 15A shows the structure of an external row address of a memory of 128 M bits, and FIG. 15B shows the structure of an external row address of a memory of 256 M bits;
FIG. 16 shows the allocation of addresses of the memory array of a semiconductor circuit device in the second embodiment according to the present invention;
FIG. 17 is a schematic diagram showing the arrangement of global data lines in the memory array shown in FIG. 16;
FIG. 18 is a schematic diagram showing the configuration of a data line select section in the second embodiment according to the present invention;
FIG. 19 is a schematic diagram showing the configuration of a data line select signal generation section in the second embodiment according to the present invention;
FIG. 20 is a schematic diagram showing the configuration of a write/read control section in the second embodiment according to the present invention;
FIG. 21 is a schematic diagram showing the configuration of an internal write/read section in the second embodiment according to the present invention;
FIG. 22 is a schematic diagram showing the arrangement of pads of a semiconductor circuit device in the third embodiment according to the present invention;
FIG. 23 is a schematic diagram showing the arrangement of a DQ pad group and DQ pads shown in FIG. 22;
FIG. 24 shows an example of the arrangement of chips when the semiconductor circuit device is assembled in a multi chip package in the third embodiment according to the present invention;
FIG. 25 is a schematic diagram showing another example of the arrangement of chips when the semiconductor circuit device is assembled in a multi chip package in the third embodiment according to the present invention;
FIGS. 26A-26D are schematic diagrams showing the arrangement of data pads used in a semiconductor circuit device in the fourth embodiment according to the present invention;
FIG. 27 is a schematic diagram showing the arrangement of data pads in the fourth embodiment according to the present invention;
FIG. 28 concretely shows the arrangement of pads of the semiconductor circuit device in the fourth embodiment according to the present invention;
FIG. 29 is a schematic diagram showing the configuration for performing a compression test in .times.32-bit structure in the semiconductor device according to the fifth embodiment of the present invention;
FIG. 30 is a schematic diagram showing the configuration for performing a compression test in .times.16-bit structure in the semiconductor device according to the fifth embodiment of the present invention;
FIG. 31 is a schematic diagram showing the configuration of a section for performing a compression operation in the semiconductor circuit device of a .times.8 bit configuration in the fifth embodiment according to the present invention;
FIG. 32 shows an example of the arrangement of data pads and compression result output pads of the semiconductor circuit device in the fifth embodiment according to the present invention;
FIG. 33 is a schematic diagram showing the arrangement of an internal data bus of a semiconductor circuit device in the sixth embodiment according to the present invention;
FIG. 34 shows the arrangement of the internal data bus shown in FIG. 33 more specifically;
FIG. 35 is a schematic diagram illustrating the connection between a memory sub-block and the internal data bus in the semiconductor circuit device in the sixth embodiment according to the present invention;
FIG. 36 is a schematic diagram illustrating the connection between the internal data bus and a memory block in .times.16 bit configuration of the semiconductor circuit device in the sixth embodiment according to the present invention;
FIG. 37 is a schematic diagram illustrating the connection between the memory sub-block and the internal data bus in .times.8 bit configuration of the semiconductor circuit device in the sixth embodiment according to the present invention;
FIG. 38 is a schematic diagram showing the allocation of data bits in a memory array in a modification of the sixth embodiment according to the present invention;
FIG. 39 is a schematic diagram showing the configuration of an internal data write/read section of a semiconductor circuit device in the modification of the sixth embodiment according to the present invention;
FIG. 40 shows an example of the configuration of a multiplexer shown in FIG. 39;
FIG. 41 is a schematic diagram illustrating the connection between an internal data bus and a global data line in .times.32 bit configuration of the semiconductor circuit device in the modification of the sixth embodiment according to the present
invention;
FIG. 42 is a schematic diagram illustrating the connection between an internal data bus and a global data line in .times.16 bit configuration of the semiconductor circuit device in the modification of the sixth embodiment according to the present
invention;
FIG. 43 is a schematic diagram illustrating the connection between a global data line and an internal data line the semiconductor circuit device in .times.8 bit configuration of the modification of the sixth embodiment according to the present
invention;
FIG. 44 is a schematic diagram showing the configuration of an internal data bus in the seventh embodiment according to the present invention;
FIG. 45 is a schematic diagram showing the arrangement of data pads of a semiconductor circuit device in the seventh embodiment according to the present invention;
FIG. 46 is a schematic diagram showing the configuration of the semiconductor circuit device in the seventh embodiment according to the present invention upon assembly of the semiconductor circuit device in a multi chip package;
FIG. 47 specifically shows the arrangement of the data pads in the seventh embodiment according to the present invention;
FIG. 48 is a schematic diagram showing a modification of the seventh embodiment according to the present invention;
FIG. 49 shows an example of the configuration of a data line switch circuit shown in FIG. 48;
FIG. 50 shows an example of the manner of bonding upon assembly into a single chip package of the semiconductor circuit device in the seventh embodiment according to the present invention;
FIG. 51 is a schematic diagram showing the configuration of the important parts of a semiconductor circuit device in the eighth embodiment according to the present invention;
FIG. 52 shows an example of the configuration of a global data line selecting multiplexer shown in FIG. 51;
FIG. 53 shows an example of the configuration of a multiplexer for a .times.8 bit structure shown in FIG. 51;
FIG. 54 shows an example of the configuration of a multiplexer for a .times.16 bit structure shown in FIG. 51;
FIG. 55 is a schematic diagram representing the correspondence between data pads and a selected memory cell of a semiconductor circuit device in the eighth embodiment according to the present invention;
FIG. 56 is a schematic diagram showing the configuration of a modification of the eighth embodiment according to the present invention;
FIG. 57 is a schematic diagram showing the configuration of a main portion of a semiconductor circuit device in the ninth embodiment according to the present invention;
FIG. 58 shows the configuration of an internal write/read circuit shown in FIG. 57 more specifically;
FIG. 59 shows an example of the configuration of a write driver shown in FIG. 58;
FIG. 60 shows an example of the configuration of a preamplifier shown in FIG. 58;
FIG. 61 shows an example of the configuration of a compressor shown in FIG. 58;
FIG. 62 shows an example of the configuration of a data input/output section of the semiconductor circuit device in the ninth embodiment according to the present invention;
FIG. 63 is a schematic diagram showing the configuration of a main portion of a semiconductor circuit device in the tenth embodiment according to the present invention;
FIG. 64 concretely represents the relationship between an internal data bus and transfer data with the configuration shown in FIG. 63;
FIG. 65 is a schematic diagram showing the configuration of the important parts of a semiconductor circuit device in a modification of the tenth embodiment according to the present invention;
FIG. 66 concretely shows the relationship between an internal data bus line and multi-bit test transfer data with the configuration shown in FIG. 65;
FIG. 67 specifically represents the correspondence between the internal data line and the transfer data during a multi-bit test in the tenth embodiment according to the present invention;
FIG. 68 is a schematic diagram showing the configuration of a main portion of a semiconductor circuit device in the eleventh embodiment according to the present invention;
FIG. 69 is a schematic diagram representing the correspondence between test data and data written to a memory cell in the eleventh embodiment according to the present invention;
FIG. 70 is a schematic diagram representing the correspondence between test data and data written to a memory cell in the eleventh embodiment according to the present invention;
FIG. 71 is a schematic diagram showing the correspondence between write data and external data in a normal operation mode in the eleventh embodiment according to the present invention;
FIG. 72 is a schematic diagram showing the configuration of a conventional single chip package;
FIG. 73 is a schematic diagram showing the arrangement of chips assembled in a conventional multi chip package; and
FIG. 74 is a schematic diagram showing the arrangement of data terminals of the multi chip package shown in FIG. 73.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
First Embodiment
FIG. 1 is a schematic diagram showing the configuration of a semiconductor circuit device in the first embodiment according to the present invention. In FIG. 1, a semiconductor chips 1 for a single chip package is used for implement a
semiconductor memory device 2 assembled into a multi chip package (MCP). Semiconductor memory chip 1 has a storage capacity of 128 M bits and a word structure of .times.16 bits.
Likewise, each of semiconductor memory chips 1a and 1b has a storage capacity of 128 M bits and a word structure of .times.16 bits. These semiconductor memory chips 1a and 1b are operated simultaneously. Therefore, semiconductor memory device 2
has a storage capacity of 256 M bits and a word structure of .times.32 bits.
On the other hand, where semiconductor memory chips 1a and 1b are set into a word structure of .times.8 bits, and are operated simultaneously, semiconductor memory device 2 has a word structure of .times.16 bits. In the case when one of
semiconductor memory chips 1a and 1b is operated, it is necessary to select a chip by the most significant bit of a row address signal. Therefore, allocation of the row address signal turns different from that for the semiconductor memory chip with a
storage capacity of 128 M bits. Thus, a semiconductor memory device having a storage capacity of 256 M bits cannot be implemented using two semiconductor memory chips the same in configuration. Therefore, in the case of increasing a storage capacity
with two semiconductor memory chips the same in configuration, semiconductor memory chips 1a and 1b are operated simultaneously.
Further, when refreshing is performed in semiconductor memory device 2, it is necessary to refresh semiconductor memory chips 1a and 1b simultaneously in parallel. In this case, current consumption increases in a refreshing operation.
Particularly in a self refresh mode, such as a power down mode, set when it is required to hold data, low current consumption is required, and the low power consumption specification cannot be met.
In addition, in case of the semiconductor memory device of 128 M bits, a 4 k refresh cycle is normally set for a refresh cycle in accordance with the specification. In case of the semiconductor memory device of 256 M bits, by contrast, when a
word structure is .times.16 bits, an 8K refresh cycle is normally set for the refresh cycle in accordance with the specification. Therefore, a memory having a storage capacity of 256 M bits and a word structure of .times.16 bits cannot be implemented
when using two memory chips each having a storage capacity of 128 M bits and a word structure of .times.8 bits.
In the 4K refresh cycle, it is required to execute a refreshing operation 4K times to refresh all memory cells once. In the 8K refresh cycle, it is required to execute a refreshing operation 8K times to refresh all memory cells once. Therefore,
in the 8K refresh cycle, the number of refresh rows is 8K while in the 4K refresh cycle, the number of refresh rows is 4K. In one refreshing operation, one refresh row is selected and refreshing is performed on the selected row. Refresh row is
designated by a refresh address and is the same as or different from a word line connecting memory cells on a row, depending on internal structure.
In the first embodiment, the 4K refresh cycle and the 8K refresh cycle can be selectively made executable in one semiconductor memory chip 1 so as to enable the switching of the refresh cycle between the 8K refresh cycle and the 4K refresh cycle
in accordance with the type of an assembling package and the word structure.
FIG. 2 is a schematic diagram showing the configuration of a main portion of a semiconductor circuit device (to be referred to as "semiconductor memory device" hereinafter) formed on semiconductor memory chip 1 (1a, 1b) shown in FIG. 1.
In FIG. 2, the semiconductor memory device includes a memory array 10 having a plurality of memory cells MC arranged in rows and columns. In memory array 10, word lines WL are arranged corresponding to the rows of memory cells MC and bit line
pairs BLP are arranged corresponding to the columns of memory cells MC. Memory cell MC is normally a one-transistor/one-capacitor type DRAM (dynamic random access memory) cell. Therefore, information is stored in a capacitor in the form of charges, so
that it is required to execute a refreshing operation of cyclically rewriting storage data in predetermined cycles.
The semiconductor memory device further includes a refresh cycle setting circuit 11 for setting a refresh cycle in accordance with the type of a package having semiconductor memory chip 1 assembled therein and a word configuration, a refresh
control circuit 12 for generating control signals necessary to execute a refreshing operation in cycles set in accordance with a refresh cycle designation signal REF8K applied from refresh cycle setting circuit 11, a row related control circuit 13 for
generating a control signal necessary to execute an operation related to the selection of a row in memory cell array 10 in accordance with the refresh control signal applied from refresh control circuit 12, and a row related circuit 14 for performing an
operation related to the selection of a row in memory array 10 in accordance with the row related control signal applied from row related control circuit 13.
Row related circuit 14 includes a word line selection/drive circuit for driving a word line WL to a selected state, a sense amplifier for sensing, amplifying and rewriting (restoring) data stored in memory cell MC connected to selected word line
WL, and a bit line precharge/equalization circuit for setting each bit line of bit line pair BLP at predetermined voltage level in a standby state.
Bit line pair BLP includes bit lines BL and ZBL for transmitting complementary data when a corresponding memory cell is selected. Memory cell MC is arranged corresponding to an intersection between one of complementary bit lines BL and ZBL and
word line WL.
In the configuration shown in FIG. 2, refresh cycle setting circuit 11 sets the refresh cycle at the 4K refresh cycle if semiconductor memory chip 1 is assembled in a single chip package and sets the refresh cycle at the 8K refresh cycle if
semiconductor memory chip 1 is assembled in a multi chip package with a word structure of .times.16 bits (a semiconductor memory chip solely has a word structure of .times.8 bits). Refresh control circuit 12 issues a refresh request in the cycles set
according to refresh cycle designation signal REF8K, updates a refresh address, generates and applies a refresh activation signal to row related control circuit 13.
Row related control circuit 13 generates various row related control signals so as to drive word line WL corresponding to the row designated by the refresh address to a selected state in a predetermined sequence in accordance with the refresh
activation signal applied from refresh control circuit 12. Row related circuit 14 executes the selection of corresponding word line WL, a sensing operation and a restoring operation (rewrite operation) in accordance with the control signals from row
related control circuit 13 and the refresh address signal in the predetermined sequence.
Therefore, in refresh control circuit 12, an interval for activating a refreshing operation in the 8K refresh cycle is set to half times the interval in the 4K refresh cycle. Accordingly, the number of refresh rows is doubled upon assembling in
a multi package. Even if semiconductor memory chips 1a and 1b are simultaneously refreshed, the refresh interval for the respective memory cells is made equal to be, for example, 64 ms. It is, therefore, possible to ensure executing a refreshing
operation to hold storage data with the same chip configuration.
Further, since the number of refresh rows is doubled, the number of sense amplifiers which operates in one refreshing operation can be halved. It is, therefore, possible to decrease the current consumption in one semiconductor memory chip in the
refreshing operation and to prevent an increase in current consumption in the refreshing operation when constructing a 256 M bit configuration memory.
FIG. 3 is a schematic diagram showing the configuration of memory cell array 10 shown in FIG. 2. As shown in FIG. 3, memory cell array 10 is divided into four banks A to D. These banks A to D are designated by bank address BA<1:0>. FIG. 3
shows an example in which bank address (0,0), (0,1), (1,0) and (1,1) of bank address BA<1:0> are allocated to banks A to D, respectively.
FIG. 4 shows the configuration of refresh control circuit 12 and row related control circuit 13 shown in FIG. 2 more specifically. In FIG. 4, the semiconductor memory device includes a command decoder 20 that decodes an external command CMD for
designating an operation mode, to generate an internal operation instruction signal. Command decoder 20 takes in and decodes command CMD applied externally at, for example, the rising edge of a clock signal, not shown, and generates the operation mode
instruction signal for specifying the operation mode designated by the command. FIG. 4 representatively shows an array activation instruction signal ACT for instructing the driving of the memory array to a selected state, a precharge instruction signal
PRE for instructing the deactivation of the selected array, a self refresh entry signal SRFEN for instructing the execution of a self refreshing operation, and a self refresh exit signal SRFEX for instructing the completion of a self refresh mode.
Refresh control circuit 12 includes a refresh timer 31 for issuing a refresh request RFREQ in a predetermined cycle when activated, a refresh execution control circuit 32 for activating refresh timer 31 in response to self refresh entry signal
SRFEN and self refresh exit signal SRFEX from command decoder 20 and generating a refresh activation signal RFACT and a refresh completion instruction signal RAPRE in accordance with refresh request RFREQ from refresh timer 31, a refresh address counter
33 for generating a refresh address QAD under the control of refresh execution control circuit 32, and a refresh region designation circuit 34 for designating a refresh region (refresh bank) in accordance with refresh address bit QAD<12> and
refresh cycle designation signal REF8K.
Refresh execution control circuit 32 activates refresh timer 31 when self refresh entry signal SRFEN is activated, and deactivates refresh timer 31 and completes a refreshing operation when self refresh exit signal SRFEX is activated. Refresh
execution control circuit 32 activates refresh activation signal RFACT when refresh request RFREQ is issued, and activates refresh completion instruction signal RFPRE when a predetermined time (time required to restore data under refresh) passes.
Refresh address counter 33 increments or decrements its count value each time a refreshing operation is executed. By way of example, refresh address counter 33 generates refresh address bits QAD<12:0> of 13 bits. FIG. 4 representatively
shows the most significant refresh address bit QAD<12> from refresh address counter 33.
Refresh region designation circuit 34 designates a refresh region (refresh bank) in accordance with refresh address bit QAD<12> when refresh cycle designation signal REF8K is active. When refresh cycle designation signal REF8K is at L
level, refresh region designation circuit 34 simultaneously activates a refreshing operation for all banks, irrespectively of the refresh address bit QAD<12>. The logical level of refresh cycle designation signal REF8K is set according to the type
of the package having the semiconductor memory device assembled therein and the word structure by mask interconnection or by fixing a potential of a mode setting pad.
Row related control circuit 13 includes a row related control signal generation circuit 21 for generating a main array activation instruction signal MACT and a main precharge instruction signal MPRE common to banks A to D in accordance with array
activation instruction signal ACT and precharge instruction signal PRE from command decoder 20 and refresh activation signal RFACT and refresh completion instruction signal REPRE from refresh execution control circuit 32, and bank control circuits 22a to
22d provided corresponding to banks A to D, respectively. Bank A control circuit 22a and bank B control circuit 22b each receive a bank designation signal /STPAB from refresh region designation circuit 34, and bank C control circuit 22c and bank D
control circuit 22d each receive a bank designation signal /STPCD from refresh region designation circuit 34.
Bank control circuit 22, which generically refer to bank A control circuit 22a to bank D control circuit 22d collectively, receives bank address BA<1:0>. In addition, each of bank control circuits 22a to 22d receives main array activation
instruction signal MACT and main precharge instruction signal MPRE.
When active, bank control circuits 22a to 22d generate array activation signals RASA to RASD for activating the row selecting operations of the corresponding banks, respectively. Bank control circuits 22a to 22d can be driven to active/inactive
states, independently of one another. In a normal operation mode, one of array activation signals RASA to RASD is activated/deactivated in accordance with bank address BA<1:0>. In a refreshing operation mode, two or four of array activation
signals RASA to RASD are simultaneously activated.
FIG. 5 is a schematic diagram showing the configuration of a row related control circuit and a row related circuit in one bank. In FIG. 5, bank control circuit 22i includes a bank decoder 41 for decoding bank address BA<1:0>, an OR gate 42
receiving a bank select signal BAi and a refresh bank designation signal /STP from bank decoder 41, an AND gate 43 receiving the output signal of OR gate 42 and main array activation instruction signal MACT, an AND gate 44 receiving main precharge
instruction signal MPRE and the output signal of OR gate 42, a set/reset flip-flop 45 set in response to the rise of the output signal of AND gate 43 and reset in response to the rise of the output signal of AND gate 44, and a row related control signal
generation circuit 46 for generating a row related control signal in a predetermined sequence in accordance with array activation signal RASi from set/reset flip-flop 45.
Bank decoder 41 may be provided commonly to bank control circuits 22a to 22d. OR gate 42 outputs an H-level signal when bank select signal BAi or refresh bank designation signal /STP attains H level. Therefore, in a designated bank, the
activation/deactivation of array activation signal RASi is executed in accordance with main array activation instruction signal MACT and main precharge instruction signal MPRE. While array activation signal RASi is active, the designated bank is kept in
a selected state and a selected word line is kept in a selected state.
Row related signal generation circuit 46 generates a bit line precharge/equalization instruction signal, a sense amplifier activation signal, a word line drive timing signal and a row decoder enable signal. In accordance with these control
signals from row related control signal generation circuit 46, an addressed row is driven to a selected state, and the data of the memory cells connected to a word line in this selected row are sensed, amplified and latched in the selected bank.
The row related circuit includes a row decoder 52 for decoding an address signal applied through a multiplexer 51 to generate a word line select signal WS when active. Row decoder 52 drives one of 4K rows arranged in a corresponding memory bank
array 50 to a selected state. In this case, by designating one row, two word lines may be driven to a selected state.
Multiplexer 51 is provided commonly to banks A to D, and selects either refresh address QAD<11:0> from refresh address counter 33 (see FIG. 4) or external address signal AD<11:0> in accordance with a select signal MX. Select signal
MX is set in a state for selecting refresh address QAD<11:0> in a refreshing operation.
FIG. 6 shows an example of the configuration of refresh region designation circuit 34 shown in FIG. 4. In FIG. 6, refresh region designation circuit 34 includes a NAND gate 34a receiving refresh address bit QAD<12> and refresh cycle
designation signal REF8K, a gate circuit 34b receiving refresh address bit QAD<12> and refresh cycle designation signal REF8K, an AND gate 34c receiving a refresh mode instruction signal REFM and the output signal of NAND gate 34a and generating
refresh region designation signal /STPAB, and an AND circuit 34d receiving refresh mode instruction signal REFM and the output signal of gate circuit 34b and generating refresh region designation signal /STPCD.
Refresh region designation signal /STPAB stops refreshing banks A and B when made active at L level. Refresh region designation signal /STPCD stops refreshing banks C and D when active at L level.
Refresh mode instruction signal REFM is set at H level in a self refresh mode and an auto refresh mode. In the self refresh mode, a refreshing operation is executed internally at pre-set cycles. In the auto refresh mode, refresh addresses are
generated internally and a refreshing operation is executed in accordance with an external auto refresh mode instruction signal ARF.
Refresh mode instruction signal REFM is set in accordance with self refresh entry signal SRFEN and self refresh exit signal SRFEX from command decoder 20 and auto refresh mode instruction signal ARF (not shown), under the control of refresh
execution control circuit 32 shown in FIG. 4. In a normal operation mode, therefore, self refresh region designation signals /STPAB and /STPCD are both at L level. In this state, as shown in FIG. 5, a bank is selected in accordance with bank select
signal BAi through OR gate 42.
When refresh cycle designation signal REF8K is set at H level to designate the 8K refresh cycle, NAND gate 34a and gate circuit 34b generates complementary signals in accordance with refresh address bit QAD<12>. Therefore, where a
refreshing operation is executed in this 8K refresh cycle, one of refresh region designation signals /STPAB and /STPCD is set at H level and the other refresh region designation signal is set at L level.
If refresh cycle designation signal REF8K is set at L level, the output signals of NAND gate 34a and gate circuit 34b are set at H level. In the refresh mode, therefore, both of refresh region designation signals /STPAB and /STPCD are set at H
level and banks A to D are refreshed in common.
Accordingly, as shown in FIG. 7A, when refresh cycle REF8K is set at H level to designate the 8K refresh cycle, banks A and B or banks C and D are simultaneously refreshed. The refresh target banks are designated in accordance with refresh
address bit QAD<12>.
As shown in FIG. 7B, where refresh cycle REF8K is set at L level, banks A to D are simultaneously refreshed. Consequently, when two semiconductor memory chips are employed to be assembled in a multi chip package, the four banks are
simultaneously refreshed along the 8K refresh cycle. In this case, current consumption during the refreshing operation in the 4K refresh cycle is the same as that in the 8K refresh cycle. Thus, a semiconductor circuit device assembled in both a signal
chip package and a multi chip package can be implemented with the same chip configuration. Therefore, even if a semiconductor memory device of 256 M bits (a word structure of .times.16 bits) is implemented using two semiconductor memory chips each of
128 bits (a word structure of .times.8 bits), for example, it is possible to execute refreshing operation without increasing current consumption in the refresh mode.
Alternatively, banks A and D or banks C and B may be refreshed simultaneously in the 8K refresh cycle. In this case, it is possible to distribute simultaneously operating circuit portions over the chip, to prevent the concentration of power and
to efficiently dissipate heat.
Further, in the 8K refresh cycle and the 4K refresh cycle, memory cells should be refreshed at, for example, 64 ms intervals. Thus, when the refresh cycle is set at the 8K refresh cycle or 4K refresh cycle, an interval for issuing a refresh
request is set at, for example | | |
