A semiconductor integrated circuit device comprises a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a semiconductor layer insulated from the semiconductor substrate by the insulating layer; source regions of a first conduction type and drain regions of the first conduction type both formed in the semiconductor layer; body regions of a second conduction type formed in the semiconductor layer between the source regions and the drain regions to store data by accumulating or releasing an electric charge; word lines formed on the body regions in electrical isolation from the body regions to extend in a first direction; bit lines connected to the drain regions and extending in a direction different from the first direction; and buried wirings formed in the insulating layer in electrical isolation from the semiconductor substrate and the semiconductor layer, said buried wirings extending in parallel with the bit lines.
A semiconductor memory device including a memory cell without a capacitor includes: a memory cell array block including first memory cells connected between a first bit line and first word lines and second memory cells connected between a second bit line and second word lines; and a reference memory cell array block including first reference memory cells connected between a first reference bit line connected to the first bit line and a first reference word line and second reference memory cells connected between a second reference bit line connected to the second bit line and a second reference word line. When the first word lines are selected, the second reference memory cells are selected, and when the second word lines are selected, the first reference memory cells are selected. Thus, each bit line includes a reference memory cell and outputs reference signal from the reference memory cell so that data can be precisely sensed during a read operation.
A semiconductor device comprising floating body memory cells performs read and write operations by selectively connecting bit lines and inverted bit lines to sense bit lines and inverted sense bit lines.
A nonvolatile ferroelectric memory device has a plurality of ferroelectric memory cells. The ferroelectric memory cells include a first double gate cell for storing a bit of datum, the first double gate cell including a ferroelectric layer and a floating channel layer, wherein a polarity state of the ferroelectric layer affects a resistance of the floating channel layer, the resistance of the floating channel layer corresponding to the bit of datum stored in the first double gate cell; and a second double gate cell selectively turned on by a potential on a selection line to supply a potential of a sense line to the first double gate cell to control read and write operations of the first double gate cell. The present invention also provides methods for operating the nonvolatile ferroelectric memory device.
