A computer system includes multiple controllers that assist in executing the Power-On Self Test (POST) sequence to minimize the time required to complete system initialization. By shifting some of the responsibilities for executing the POST sequence to other controllers within the system, the testing and initialization of system devices can proceed concurrently. The controllers interface with peripheral devices, and include a register set that includes command information for initializing the testing and initialization of associated peripherals. The register set also includes dedicated bits for indicating the status of testing and initialization cycles, which can be read by the CPU to determine if testing or initialization is in progress, if it has completed, and if any errors have occurred. The register set also includes a configuration register for indicating configuration information and operating parameters of the initialized drive or peripheral. By distributing the testing and initialization responsibilities to the controllers, execution of the BIOS system software or system initialization software can be expedited, thus minimizing down time caused by initializing the computer system.
Provided are a method, system, and program for concurrent processing of operations in a boot sequence. A first processor signals a second processor to begin initialization and initializes computer resources. The second processor issues commands to initialize at least one storage device to place the at least one storage device in an operable state in response to the signaling by the first processor. The first process determines that one storage device including an operating system loader is operable and loads the operating system from the storage device including the operating system loader in response to determining that the storage device including the operating system loader is operable.
A memory system includes multiple memory modules, which communicate with a memory controller over one or more channels. When a memory module receives an initialization command from a processor or the memory controller, the memory module performs an initialization procedure of the memory locations associated with the memory module. In an embodiment, at least a portion of the initialization procedure is performed in parallel with the other memory modules performing initialization procedures. Each memory module may include a buffer module, which receives the initialization command, and generates and sends data packets with the initialization data to the memory locations. A memory module also can receive a test command from the processor or memory controller, which causes the memory module to read data from the memory locations, compare that data with expected data, and keep track of any errors that may occur.
