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Claims  |
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What is claimed is:
1. A method for emulating individual devices in a multiple device chain, said method comprising: obtaining the topology of the chain; selecting one device within the chain by
generating a selection instruction and sending the selection instruction to the chain; placing at least one other device within the chain into bypass mode; sending emulation instructions to the chain, wherein the emulation instructions bypass the at
least one other device and are executed by the one device; wherein the individual devices comprise JTAG devices and the chain includes a boundary scan chain; and wherein the selection instruction comprises; an Instruction Register Header field to
retain the number of instruction register bits upstream of the one device in the scan chain; an Instruction Register Tail field to retain the number of instruction register bits downstream of the one device in the scan chain; a Data Register Header
field to retain the number of devices upstream of the one device in the scan chain; a Data Register Tail field to retain the number of devices downstream of the one device in the scan chain; and a Command field to retain a command for the one device.
2. The method of claim 1, wherein said obtaining the topology, said selecting, and said placing, are effected by the emulator.
3. The method of claim 1, wherein said selecting comprises generating a selection instruction and sending the selection instruction to the scan chain.
4. The method of claim 1, wherein the emulator includes a DEVNUM register to receive the selection instruction.
5. The method of claim 1, wherein said placing comprises generating a bypass instruction and sending the bypass instruction to the scan chain.
6. The method of claim 5, wherein the emulator includes a DEVALT register to receive the bypass instruction.
7. A method for emulating individual devices in a multiple device chain, said method comprising; obtaining the topology of the chain; selecting one device within the chain; placing at least one other device within the chain into bypass mode
by generating bypass instruction and sending the bypass instruction to the scan chain; sending emulation instructions to the chain, wherein the emulation instructions bypass the at least one other device and are executed by the one device; wherein the
individual devices comprise JTAG devices and the chain includes a boundary scan chain; and wherein the bypass instruction comprises; an Instruction Register Header field to retain the number of instruction register bits upstream of the other device in
the scan chain; an Instruction Register Tail field to retain the number of instruction register bits downstream of the other device in the scan chain; a Data Register Header field to retain the number of devices upstream of the other device in the scan
chain; a Data Register Tail field to retain the number of devices downstream of the other device in the scan chain; and a Command field to retain a command for the one device.
8. The method of claim 1, wherein said sending emulation instructions includes placing the one device into a data mode.
9. The method of claim 8, wherein said sending emulation instructions includes formatting the emulation instructions to compensate for the at least one other device.
10. The method of claim 9, wherein said formatting includes compensating for bits added by the at least one other device.
11. The method of claim 1, wherein said obtaining the topology includes automatically determining the topology of the scan chain.
12. The method of claim 1, wherein the topology includes the number of devices in the scan chain, and the number of instruction register bits in each of the devices.
13. The method of claim 12, wherein the topology includes a device number for at least one of the devices within the scan chain.
14. The method of claim 1, wherein said selecting includes serially placing an instruction register of the one device into the scan chain.
15. The method of claim 1, wherein the emulator includes a debugger.
16. The method of claim 15, further comprising displaying a graphical representation of the scan chain.
17. The method of claim 16, wherein the graphical representation includes the topology of the scan chain.
18. The method of claim 17, wherein the topology includes the number of devices in the scan chain, and the number of instruction register bits in each of the devices.
19. The method of claim 16, wherein the graphical representation includes a device number for at least one of the devices within the scan chain.
20. The method of claim 1, further comprising coupling an emulator to the chain.
21. An emulator comprising: an emulator connector configured to couple to a scan chain; a topology module configured to obtain the topology of the scan chain; a selection module configured to select one device within the scan chain; a bypass
module configured to place at least one other device within the scan chain into bypass mode; an emulation instruction module configured to send emulation instructions to the scan chain; and a translation module configured to translate the emulation
instructions into a format usable by the one device; wherein the emulation instructions bypass the at least one other device and are executed by the device.
22. The emulator of claim 21, comprising a graphical user interface (GUI), said GUI comprising: a user-selectable list of devices; a graphical display of the chain; and at least one chain parameter field.
23. The GUI of claim 22, wherein the individual devices comprise JTAG devices and the chain includes a boundary scan chain.
24. The GUI of claim 23, wherein said at least one device parameter field displays a parameter selected from the group consisting of: number of devices in the scan chain; number of instruction register bits in the scan chain; and a device
number for at least one of the devices.
25. The GUI of claim 23, wherein said at least one device parameter field comprises a Number of Devices field, a Total Instruction Register Bit field, and a Device Number field.
26. The GUI of claim 25, wherein said Device Number field comprises a decimal format field and a hexadecimal format field.
27. The GUI of claim 23, wherein the graphical display comprises the number of devices in the scan chain, the model number of each device, the Instruction Register length of each device, and relative position of each device within the scan
chain.
28. A system for emulating individual JTAG devices in a multiple device boundary scan chain, said system comprising: a topology module configured to obtain the topology of the scan chain; a selection module configured to select one device
within the scan chain; a bypass module configured to place at least one other device within the scan chain into bypass mode; and
an emulation instruction module configured to send emulation instructions to the scan chain, wherein the emulation instructions bypass the at least one other device and are executed by the one device;
wherein the bypass module is configured to generate a bypass instruction including: an Instruction Register header field to retain the number of instruction register bits upstream of the other device in the scan chain; an Instruction Register
Tail field to retain the number of instruction register bits downstream of the other device in the scan chain; a Data Register Header field to retain the number of devices upstream of the other device in the scan chain; a Data Register Tail field to
retain the number of devices downstream of the other device in the scan chain; and a Command field to retain a command for the one device.
29. An article of manufacture for emulating individual JTAG devices in a multiple device boundary scan chain, said article of manufacture comprising: a computer usable medium having a computer readable program code embodied therein, said
computer readable program code including instructions for: obtaining a topology of the scan chain; selecting one device within the scan chain; placing at least one other device within the scan chain into bypass mode; and sending emulation instructions
to the scan chain, wherein the emulation instructions bypass the at least one other device and are executed by the one device; wherein said instructions for placing include a bypass instruction including: an Instruction Register Header field to retain
the number of instruction register bits upstream of the other device in the scan chain; an Instruction Register Tail field to retain the number of instruction register bits downstream of the other device in the scan chain; a Data Register Header field
to retain the number of devices upstream of the other device in the scan chain; a Data Register Tail field to retain the number of devices downstream of the other device in the scan chain; and a Command field to retain a command for the one device.
30. Computer readable program code for emulating individual JTAG devices in a multiple device boundary scan chain, said computer readable program code comprising instructions to perform the following steps: obtaining the topology of the scan
chain; selecting one device within the scan chain; placing at least one other device within the scan chain into bypass mode; and
sending emulation instructions to the scan chain, wherein the emulation instructions bypass the at least one other device and are executed by the one device;
wherein the instructions for placing include a bypass instruction including: an Instruction Register Header field to retain the number of instruction register bits upstream of the other device in the scan chain; an Instruction Register Tail
field to retain the number of instruction register bits downstream of the other device in the scan chain; a Data Register Header field to retain the number of devices upstream of the other device in the scan chain; a Data Register Tail field to retain
the number of devices downstream of the other device in the scan chain; and a Command field to retain a command for the one device.
31. A system for emulating individual JTAG devices in a multiple device boundary scan chain, said system comprising: a topology module configured to obtain the topology of the scan chain; a selection module configured to select one device
within the scan chain; a bypass module configured to place at least one other device within the scan chain into bypass mode; an emulation instruction module configured to send emulation instructions to the scan chain, wherein the emulation instructions
bypass the at least one other device and are executed by the one device; at least one register configured to receive selection and bypass instructions respectively generated by the selection and bypass modules; and a graphical user interface (GUI)
including: a user-selectable list of JTAG devices; a graphical display of the scan chain; and at least one scan chain parameter field.
32. The emulator of claim 21, wherein said translation module comprises a FPGA disposed within said emulator connector. |
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Claims |
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Description |
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BACKGROUND
Since the mid-1970s, the structural testing of loaded printed circuit boards (PCBs) has relied very heavily on the use of the so-called in-circuit "bed-of-nails" technique (FIG. 1). This method of testing makes use of a fixture containing a
bed-of-nails to access individual devices on the board through test lands laid into the copper interconnect, or other convenient contact points. Testing then generally proceeds in two phases: the power-off tests followed by power-on tests.
Power-off tests check the integrity of the physical contact between nail and the on-board access point. They then may carry out open and shorts tests based on impedance measurements. Power-on tests apply stimulus to a chosen device on a board,
with an accompanying measurement of the response from that device. Other devices that are electrically connected to the device-under-test are usually placed into a safe state (a process called "guarding"). In this way, the tester is able to check the
presence, orientation, and bonding of the device-under-test in place on the board.
Fundamentally, the in-circuit bed-of-nails technique relies on physical access to all devices on a board. For plated-through-hole technology, the access is usually gained by adding test lands into the interconnects on the "B" side of the
board--that is, the solder side of the board. The advent of surface mount devices meant that manufacturers began to place components on both sides of the board--the "A" side and the "B" side. The smaller pitch between the leads of surface-mount
components caused a corresponding decrease in the physical distance between the interconnects. This had serious impact on the ability to place a nail accurately onto a target test land. The question of access was further compounded by the development
of multi-layer boards.
In the 1980s a group known as the Joint Test Action Group (JTAG) examined the problem and its possible solutions. Their preferred method of solution was based on the concept of placing a series of cells forming a serial shift register, around
the boundary of the device. This shift register became known as a boundary-scan register. The JTAG approach ultimately became an international standard known as the IEEE 1149.1 "Test Access Port and Boundary-Scan Architecture". As used herein, the
terms "JTAG", "JTAG compliant", and/or "IEEE 1149.1" are interchangeably used to refer to this standard (including subsequent revisions and modifications thereof) and/or devices that are compliant with this standard.
The boundary-scan cells forming the boundary-scan register essentially formed a series of "virtual nails", which may be used in a manner similar to the actual nails discussed above to test the presence, orientation, and bonding of devices in
place on a board. In particular, the prime function of the bed-of-nails in-circuit tester, and thus, the boundary-scan architecture, has been to test for manufacturing defects, such as missing devices, damaged devices, open and short circuits,
misaligned devices, and wrong devices.
It was assumed that devices had already been tested for functionality when they existed only as devices (i. e., prior to assembly on the board). Boundary-scan architecture was viewed as an alternative way of testing for the presence of
manufacturing defects, including defects caused by shock, such as electrical shock (e. g., electrostatic discharge), mechanical shock (e. g., clumsy handling), or thermal shock (e. g., hot spots caused by the solder operation). A defect, if it occurs,
is likely present either in the periphery of the device (leg, bond wire, driver amplifier), in the solder, or in the interconnect between devices. It is very unusual to find damage to the core logic without there being some associated damage to the
periphery of the device. In-circuit testers thus generally were not configured or intended to prove the overall functionality of the devices.
However, with the proliferation of complex board mounted systems, it is often desirable to effect in-depth testing of individual components. A need thus exists for a method and apparatus for emulating and/or debugging individual devices using
existing scan chain architecture.
SUMMARY
According to an embodiment of this invention, a method is provided for emulating individual JTAG devices in a multiple device boundary scan chain. The method includes coupling an emulator to the scan chain, and obtaining the topology of the scan
chain. One device within the scan chain is then selected, and at least one other device within the scan chain is placed into bypass mode. Emulation instructions are sent to the scan chain, so that the emulation instructions bypass the at least one
other device and are executed by the one device.
In another aspect, the present invention includes a graphical user interface (GUI) for an emulator configured to emulate individual JTAG devices in a multiple device boundary scan chain. The GUI includes a user-selectable list of devices, a
graphical display of the scan chain, and at least one scan chain parameter field.
A further aspect of the present invention includes a system for emulating individual JTAG devices in a multiple device boundary scan chain. The system includes an emulator couplable to the scan chain, and a topology module configured to obtain
the topology of the scan chain. The system also includes a selection module configured to select one device within the scan chain, and a bypass module configured to place at least one other device within the scan chain into bypass mode. An emulation
instruction module is configured to send emulation instructions to the scan chain, so that the emulation instructions bypass the at least one other device and are executed by the one device.
A still further aspect of this invention includes an article of manufacture for emulating individual JTAG devices in a multiple device boundary scan chain, the article of manufacture including a computer usable medium having a computer readable
program code embodied therein. The computer usable medium includes computer readable program code configured for integration with an emulator, the emulator being couplable to the scan chain. This aspect further includes computer readable program code
for obtaining the topology of the scan chain, and computer readable program code for selecting one device within the scan chain. Computer readable program code is also provided for placing at least one other device within the scan chain into bypass
mode. Computer readable program code is also provided for sending emulation instructions to the scan chain, so that the emulation instructions bypass the at least one other device and are executed by the one device.
BRIEF DESCRIPTION OF THE
DRAWINGS
The above and other features and advantages of this invention will be more readily apparent from a reading of the following detailed description of various aspects of the invention taken in conjunction with the accompanying drawings, in which:
FIGS. 1 to 5 are schematic representations of various aspects of boundary scan architecture of the prior art;
FIG. 6 is a schematic representation of an exemplary boundary scan chain used in connection with embodiments of the present invention;
FIG. 7A is a schematic representation of an embodiment of the present invention, including an exemplary boundary scan chain;
FIG. 7B is a block diagram of an embodiment of a method of emulating a device, in accordance with the present invention, with optional portions thereof shown in phantom;
FIG. 7C is a block diagram of the emulator of the embodiment of FIG. 7A; and
FIGS. 8-12 are screen displays of a graphical user interface of the present invention.
DETAILED DESCRIPTION
Referring to the figures set forth in the accompanying drawings, the illustrative embodiments of the present invention will be described in detail hereinbelow. For clarity of exposition, like features shown in the accompanying drawings shall be
indicated with like reference numerals and similar features as shown in alternate embodiments in the Drawings shall be indicated with similar reference numerals.
Embodiments of the present invention include an emulator 110 and software therefor, which enables devices on a multiple device scan chain to be individually targeted for emulation/debugging operations. Particular embodiments of the present
invention include JTAG compliant instructions that utilize boundary scan input and output cells to selectively bypass individual devices in the serial scan chain, to enable one or more selected devices to be coupled through the scan chain to the
emulator/debugger 110. Examples of JTAG enabled (also referred to as JTAG compliant) devices that may be used in conjunction with embodiments of the present invention include the 6xx , 7xx and 82xx family of processors available from Motorola.RTM.
(Palatine, Ill.), as well as POWERPC.RTM. (International Business Machines Corporation `IBM`, Armonk, N.Y.), 4xx (IBM), MIPS.RTM. (Mips Technologies, Inc., Mountain View, Calif.), and ARM (Arm Limited, Cambridge, England) processors.
Alternate embodiments of the present invention may be used with other types of devices, such as IEEE 1149.1 compatible devices capable of in-circuit PAL, FLASH and FPGA programming. These alternative embodiments may provide features such as
boundary scan signal display and in-circuit testing.
Where used in this disclosure, the term "emulator" is used in a manner familiar to those skilled in the art, namely, to refer to hardware and/or software configured to enable a host processor to run software designed for a target processor, and
which may include a source-level debugger. For example, the term "emulator" may include the visionICE.TM. real-time in-circuit emulator, and/or visionPROBE.TM. hardware-assisted debugging & test tool products available from Wind River Systems, Inc.
(Alameda, Calif.) alone or in combination. These products typically include a translation module (not shown), e.g., a Field Programmable Gate Array or the like, configured to translate emulation/debugging instructions into a format, such as JTAG, which
is usable by the target device(s). Such an emulator, modified in accordance with embodiments of the present invention as described herein, is referred to as "emulator 110".
Referring now to Figures, the apparatus of the present invention will be more thoroughly described. Prior to discussing the configuration and function of embodiments of this invention, a brief discussion of JTAG boundary-scan architecture and
operation is in order.
Turning to FIG. 1, in a JTAG compliant device 30, each primary input 40 and primary output 42 signal is supplemented with a multi-purpose memory element known as a boundary-scan cell 44. Cells 44 coupled directly to primary inputs 40 are
generally referred to as "input cells." Similarly, cells 44 coupled directly to primary outputs 42 are referred to as "output cells." As used herein, when distinguishing between elements within a device, the terms "input" and "output" are defined
relative to the core logic 46 of the device. The terms "input" and "output" may also be used herein to reference particular interconnects between two or more devices.
The collection of boundary-scan cells 44 is configured as a parallel-in, parallel-out shift register. A parallel load operation, referred to as a "capture" operation, causes signal values on device input pins 40 to be loaded into the input cells
and, signal values passing from the core logic 46 to device output pins 42 to be loaded into the output cells. A parallel unload operation--called an "update" operation--causes signal values already present in the output scan cells to be passed out
through the device output pins 42. Signal values already present in the input scan cells will be passed into the core logic 46.
Data may also be shifted around the shift register, in serial mode, starting from a dedicated device input pin referred to as "Test Data In" (TDI) pin 48 and terminating at a dedicated device output pin referred to as "Test Data Out" (TDO) pin
50. A test clock, TCK, is fed into clock pin 52 and the mode of operation is controlled by a dedicated "Test Mode Select" (TMS) pin 54.
At the device level, the boundary-scan elements 44 generally do not contribute to the functionality of the core logic 46. Rather, the boundary-scan path 62 (FIG. 2) is independent of the function of the device 30. The benefit of the scan path
62 is at the board level as shown in FIG. 2.
Turning now to FIG. 2, an exemplary board 60 contains four boundary-scan devices 30. The board 60 includes an edge-connector TDI input 64 connected to the TDI 48 of the first device. TDO 50 of the first device is connected to TDI 48 of the
second device, and so on, creating a global scan path 62 terminating at an edge connector TDO output 66. TCK input 68 is connected in parallel (not shown) to each device TCK 52. TMS 70 is similarly connected in parallel (not shown) to each TMS 54.
Particular tests may be applied to the device interconnects via the global scan path 62--by loading the stimulus values into the appropriate device-output scan cells 44, by the process of entering a value into the edge connector TDI input 64
(i.e., using a "shift-in" operation), applying the stimulus ("update" operation), capturing the responses at device-output scan cells ("capture" operation), and shifting the response values out to the edge connector TDO (shift-out operation).
Using the boundary-scan cells to test the core functionality is called "internal test," shortened to Intest. Using the boundary-scan cells to test the interconnect structure between two devices is called "external test," shortened to Extest.
The use of the cells for Extest is the major application of boundary-scan architecture, searching for opens and shorts plus damage to the periphery of the device. Intest has only typically been used for very limited testing of the core functionality (i.
e., an existence test, to identify defects such as devices missing, incorrectly oriented, or misalignment.
Turning now to FIG. 3, the JTAG architecture is shown in greater detail. As shown, device 30 includes Test Data In (TDI) 48, Test Mode Select (TMS) 54, Test Clock input (TCK) 52, Test Data Out (TDO) 50--and an optional test pin Test Reset (TRST)
76. These pins are collectively referred to as the Test Access Port (TAP).
A boundary-scan cell 44 directly coupled to each device primary input and primary output pin (not shown), are interconnected internally to form a serial boundary-scan register (Boundary Scan) 84.
Additional features include a finite-state machine TAP controller 86 having inputs coupled to TCK 52, TMS 54, and optionally, TRST 76. An n-bit Instruction Register (IR) 88 is provided to hold a current instruction. A 1-bit bypass register
(Bypass) 90 is provided, and optionally | | |
