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High speed methods for maintaining a summary of thread activity for multiprocessor computer systems
   
Document Number
US Patent 6886162
Issued Date
April 26, 2005
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Abstract
A high-speed method for maintaining a summary of thread activity reduces the number of remote-memory operations for an n processor, multiple node computer system from n.sup.2 to (2n-1) operations. The method uses a hierarchical summary of-thread-activity data structure that includes structures such as first and second level bit masks. The first level bit mask is accessible to all nodes and contains a bit per node, the bit indicating whether the corresponding node contains a processor that has not yet passed through a quiescent state. The second level bit mask is local to each node and contains a bit per processor per node, the bit indicating whether the corresponding processor has not yet passed through a quiescent state. The method includes determining from a data structure on the processor's node (such as a second level bitmask) if the processor has passed through a quiescent state. If so, it is then determined from the data structure if all other processors on its node have passed through a quiescent state. If so, it is then indicated in a data structure accessible to all nodes (such as the first level bitmask) that all processors on the processor's node have passed through a quiescent state. The local generation number can also be stored in the data structure accessible to all nodes. If a processor determines from this data structure that the processor is the last processor to pass through a quiescent state, the processor updates the data structure for storing a number of the current generation stored in the memory of each node.
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High speed methods for maintaining a summary of thread activity for multiprocessor computer systems - US Patent 6886162 Drawing
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Number of Claims:
10
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Published
April 26, 2005
Application Number
09/127,085
Filed
July 31, 1998
US Classification
718/102   711/124 711/147 711/149 711/158 718/106 718/107
Int'l Classification
G06F   9/00   (20060101)  
Examiner
Attorney/Law Firm
Parent Case
RELATED APPLICATION DATA This application is based on provisional U.S. Patent Application Ser. No. 60/057,251, filed Aug. 29, 1997.
USPTO Field of Search
718/100   718/102   718/104   718/106   718/107   711/120   711/121   711/124   711/147   711/149   711/158   709/100   709/101   709/102   709/103   709/104   709/106   709/108   709/105  
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