A power supply device has a reference voltage generator for generating a reference voltage, a monitor voltage generator for generating a monitor voltage that varies according to an output voltage, an output controller for producing the output voltage from an input voltage in such a way that the monitor voltage is kept equal to the reference voltage and then supplying the output voltage to a load, and a reference voltage adjuster for varying the reference voltage according to the monitor voltage. This makes it possible to reduce, with a simple configuration, variation in the output voltage resulting from variation in the power source or the load.
A transistor drive circuit, a constant voltage circuit, and a method thereof provided with a reference voltage generator, a power voltage detector, and a plurality of error amplifying circuits. The plurality of error amplifying circuits have different operational characteristics. One of the error amplifying circuits is selectively activated in response to a control signal in accordance with an operational mode selected. A reference voltage produced by the reference voltage generator or a divided voltage produced by the power voltage detector is also changed in response to the control signal suitably for each one of the plurality of error amplifying circuits which is selectively activated so as to control the power voltage generated by a power transistor to output a constant power voltage.
A PMU that includes LDOs is provided. The PMU also includes, for each LDO, a corresponding reference circuit that provides a reference voltage for the LDO. Further, the PMU includes a central bias circuit that provides a reference current to each of the voltage reference circuits. Each reference circuit includes a delay circuit, a counter, a binary-weighted resistor ladder, and switches coupled to the resistor ladder. In each reference circuit, the resistor ladder provides the corresponding reference voltage from the received reference current. Further, the counter controls the switches to "step up" the reference voltage in a well-defined manner during the power-up sequence. The reference voltage is stepped up from a minimum voltage to a final reference voltage by one least significant bit at each clock pulse. Also, the delay circuits are employed to control when each reference voltage begins to increase from the minimum voltage.