A low drop-out voltage regulator uses a voltage subtractor circuit 36 to form a power supply rejection boost circuit. The voltage subtractor 36 is inserted between the pass element 20 and the amplifier 26 of the low drop-out regulator. The voltage regulator circuit includes a pass element 20 coupled between an input node and an output node; a voltage feedback circuit 28 and 30 coupled to the output node Vo; an amplifier 26 having an input coupled to the voltage feedback circuit; and a voltage subtractor 36 having a control node coupled to an output of the amplifier 26, an output coupled to a control node of the pass element 20, and an input coupled to the input node. The boost circuit improves supply noise rejection performance significantly without adding much complexity to the regulator system. The boost circuit is simple and consumes negligible silicon area and power.
One embodiment of the invention is a hybrid boost regulator that includes a conventional boost regulator chip that operates when its input voltage is above 2.5 volts and a pre-boost circuit that operates when its input voltage is above 1 volt. A single 1.5 volt battery may be used to power the hybrid boost regulator. The pre-boost circuit is connected to the voltage input terminal of the boost regulator chip. The pre-boost circuit boosts the battery voltage (e.g., 1.5v) at an output terminal of the hybrid boost regulator to approximately the minimum operating voltage (e.g., 2.5v) of the boost regulator chip. Since this pre-boosted voltage is applied to the voltage input terminal of the boost regulator chip, the boost regulator chip will become operational when the ramping output voltage of the hybrid boost regulator exceeds about 2.5 volts. Once the boost regulator chip is operational, the pre-boost circuit is then turned off, and the boost regulator chip runs off the 1.5 volt power supply to ramp up the output voltage to the full regulated voltage.
A system and a method are disclosed for providing a highly efficient wide bandwidth power supply for a power amplifier. A power supply control circuit of the invention comprises a wide bandwidth low drop out (LDO) circuit and a highly efficient switcher circuit. The switcher circuit comprises a switcher control circuit that receives an I.sub.LDO current signal from the low drop out (LDO) circuit and an I.sub.SWITCHER current signal from the switcher circuit. The switcher control circuit uses the I.sub.LDO value and the I.sub.SWITCHER value to control an amount of current that is provided by the switcher circuit. The I.sub.LDO current from the low drop out (LDO) circuit and the I.sub.SWITCHER current from the switcher circuit are used to control a supply voltage V.sub.CC that is provided to a power amplifier.
A power supply circuit includes an output driver transistor, a reference voltage generator circuit, an output voltage detector circuit, an amplifier circuit, and a buffer circuit. The output driver transistor outputs a current in accordance with a first control signal input thereto. The reference voltage generator circuit generates a predetermined reference voltage. The output voltage detector circuit detects an output voltage and outputs a divided voltage generated based on the output voltage. The amplifier circuit has a first polarity and a second polarity opposite to the first polarity and compares the predetermined reference voltage and the divided voltage and outputs a second control signal. The buffer circuit receives the second control signal and controls the operation of the output driver transistor in accordance with the second control signal. The buffer circuit includes first and second transistors having a polarity same as the second polarity of the amplifier circuit.
