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Polishing pad apparatus and methods
   
Document Number
US Patent 6899612
Issued Date
May 31, 2005
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Abstract
Polishing pads having a surface morphology that results in a high degree of planarization efficiency when planarizing a wafer surface are disclosed. One conditioned polishing pad is non-porous and has a surface height distribution with a surface roughness Ra<3 microns. Another conditioned polishing pad is porous and has a surface height probability distribution with a pad surface height Ratio R.gtoreq.60%, or alternatively has an asymmetric surface height probability distribution characterized by an asymmetry factor A.sub.10.ltoreq.0.50. Methods of pad conditioning and planarizing a wafer using the polishing pads are also disclosed.
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Number of Claims:
5
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Published
May 31, 2005
Application Number
10/373,513
Filed
February 25, 2003
US Classification
451/527   451/539
Int'l Classification
B24B   37/04   (20060101)   B24B   53/007   (20060101)  
Examiner
Attorney/Law Firm
USPTO Field of Search
451/527   451/539   451/285   451/286   451/287   451/288   451/289   451/56   451/443   451/444   51/298  
Related Patents
7569268 - Chemical mechanical polishing pad - Owned by Rohm and Haas Electronic Materials CMP Holdings, Inc. (Newark, DE)

The polishing pad is suitable for planarizing at least one of semiconductor, optical and magnetic substrates. The polishing pad has an ultimate tensile strength of at least 3,000 psi (20.7 MPa) and polymeric matrix containing closed cell pores. The closed cell pores have an average diameter of 1 to 50 .mu.m and represent 1 to 40 volume percent of the polishing pad. The pad texture has an exponential decay constant, .tau., of 1 to 10 .mu.m as a result of the natural porosity of the polymeric matrix and a surface texture developed by implementing periodic or continuous conditioning with an abrasive. The surface texture has a characteristic half height half width, W.sub.1/2 that is less than or equal to the value of .tau..

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