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Mechanism for enabling efficient execution of an instruction
   
Document Number
US Patent 6904516
Issued Date
June 7, 2005
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Inventors
Lam; Ioi K. (Mountain View, CA)
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Abstract
A mechanism is provided for execution of an instruction having one or more parameters that need to be resolved at runtime. Instructions being executed may be stored in non-rewritable storage. The present invention allows costly parameter resolution to be circumvented during subsequent executions of the same instruction. An interpreter invokes an optimization module when it encounters an instruction with one or more associated parameters that need to be resolved at runtime. If the optimization module determines that resolved values associated with the instruction are available in a cache, then optimization module obtains resolved values associated with the instruction from the cache. Resolving parameters into their corresponding object references is time-consuming and utilizes valuable computer resources. By obtaining resolved values stored during a previous execution of an instruction, the optimization module avoids repeatedly resolving parameters associated with an instruction. This enables efficient execution of an instruction.
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Number of Claims:
51
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Owner
Sun Microsystems, Inc. (Santa Clara, CA)
Published
June 7, 2005
Application Number
10/198,446
Filed
July 17, 2002
US Classification
712/227   717/139
Int'l Classification
G06F   9/45   (20060101)   G06F   9/30   (20060101)  
USPTO Field of Search
712/227   717/139  
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In a program executing apparatus, a code reading section reads intermediate codes into a storage unit. A data-reference analyzing section determines whether the operands of instructions in the intermediate codes stored in the storage unit require a data reference. Each data reference is analyzed for instructions requiring the data reference. A code rewriting section rewrites the operands of the instructions according to the analysis information obtained by the data-reference analyzing section. An address updating section updates the addresses of address-related instructions. After all intermediate codes are interpreted, a main interpreting and executing section starts interpreting and executing the intermediate codes.

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