An aspect of the present invention reduces droop in the reference signal provided to ADCs. A compensation resistor of appropriate resistance value is provided in the path of the reference signal to minimize the droop.
CROSS REFERENCE TO RELATED APPLICATIONS
The present invention claims priority from pending provisional application Ser. No. 60/498,494, Filed on: Aug. 28, 2003, entitled, "Piecewise linear calibration to correct transfer function errors of digital to analog converter", and is incorporated in its entirety herewith.
Providing a substantially constant reference voltage to a component from a reference buffer connected by a path. The load that would be offered to the reference buffer in desired durations is estimated, and a dummy load is added to the path such that the aggregate load on the path is approximately constant. In case of the stages of an ADC, the sub-code generated by each stage during a sampling phase is used to estimate the load that would be offered, and the dummy load is added in the hold phase to keep the reference voltage constant in the hold phase, as desired.
A semiconductor integrated circuit includes a first external terminal for receiving a voltage converted by a resistance portion from a current varying in response to an extrinsic factor, a second external terminal for externally outputting the voltage received at the first external terminal as a detection signal, a control circuit outputting a control signal for changing a resistance value of the resistance portion based on the voltage received at the first external terminal, and a third external terminal for outputting the control signal to the resistance portion.
