A column slice of a CMOS TDI sensor includes a column bus, a column of pixels, plural first switches, a column of accumulators, plural second switches, plural third switches and output bus 39. Each of the plural first switches is coupled between the column bus and a corresponding pixel of the column of pixels, and each of the plural second switches is coupled between the column bus and a corresponding accumulator of the column of accumulators. In operation, only one switch at a time of plural first switches is "on" to connect the voltage signal from a corresponding pixel to the column bus while all remaining plural first switches are "off" to isolate the column bus from all remaining pixels. Only one of the plural second switches is "on" to connect the signal on the column bus to an accumulator while all remaining plural second switches are "off" to isolate the bus from all remaining accumulators. A main control circuit includes first and second shift registers to control the plural first and second switches to couple a signal from each pixel of the column of pixels into a corresponding accumulator of the column of accumulators while updating the accumulator until signals from all pixels have been transferred into corresponding accumulators. After this update cycle, an accumulated signal from the one accumulator that is currently addressed by a third shift register is read to the output. Then, the first and third shift registers are incremented. A new update cycle begins when a point in a moving image focused on the column slice crosses a pixel boundary. The same pattern repeats continuously. Valid TDI data is produced at the output after a number of full cycles of the transfer of pixels signals to the accumulators has been complete, the number being equal to the number of pixels.
A circuit includes a circuit chip and a plurality of clock drivers external to the circuit chip. The circuit chip includes a plurality of isolated clocking subunits and a corresponding plurality of terminals. Each clocking subunit is electrically isolated from any other clocking subunit. Each clocking subunit is coupled to a respective terminal. For each of the plurality of terminals, an output from one and only one clock driver of the plurality of clock drivers is coupled to the corresponding terminal of the plurality of terminals, and inputs of all clock drivers are coupled together.
