The object of the invention is to provide a method of manufacturing a semiconductor device and a processing apparatus for planarization wherein to form copper wiring in multiple layers. The removal of a residue of polishing by local electro polishing, the enhancement of the performance of planarization by using a grindstone and the reduction by small frictional force in electro polishing of damage, are enabled. To achieve the object, the following measures are taken. A residue of polishing of copper is removed by combining the detection of a local area including the residue of polishing of copper and local processing for electro polishing. As small-load processing for planarization is enabled by using electro polishing, multilayer interconnection structure using low-k material as a dielectric interlayer is also enabled. Plural pairs of small unit electrodes in a pair of which minus electrodes surround a plus electrode are provided to a tool for electro polishing, each electrode is connected to a power supply, pulse voltage is applied to each electrode and copper is electrolytically polished.
An electrostatic chuck structure for holding an article is presented. The chuck structure comprises an electrically insulating chuck body layer having a first flat surface for holding the article thereon, and a second opposite surface having a honeycombed pattern in the form of an array of spaced-apart grooves. This second patterned surface of the chuck body surface for depositing thereon an electrically conductive layer (electrodes). A dielectric spacer between the electrodes and the article on the chuck body layer is defined by a portion of the chuck body layer between the grooves' bottom and the flat surface.
