A memory, such as a register file or a cache, having stack pMOSFETs shared among its word line drivers, where a stack pMOSFET shared by a set of word line drivers has its drain connected to the sources of the pMOSFETs in the set or word line drivers, and were each stack pMOSFET is controlled by an enable signal so as to turn ON only if its corresponding set of word line drivers is enabled. The enable signal may be provided by a write or read enable port, or by the memory's address decoder. The stacked configuration of pMOSFETs significantly reduces sub-threshold leakage current in the word line drivers with very little penalty in performance.
At least one transistor (MPX) is connected between a plurality of word line driving element circuits formed by using CMOS inverters (MP0 and MN0, etc.) and a source potential (Vcc). This transistor (MPX) is independently controlled by a control signal (DECENB) separate from control signals (AB-0 to AB-n) of the word line driving element circuits and has both a through current preventing function by adjusting timing and a peak current reducing function by limiting an electric current. Even when all word lines (SWL0 to SWLn) are driven at the same time, the electric current is limited and the peak current is suppressed.
