Complex control procedures employ direct memory access by a first DMA processing unit 54 to send control data to a first controller by means of DMA channels 54.sub.-1 to 54.sub.-n, and by a second DMA processing unit 56 to send control data to a second controller 36 by means of DMA channels 56.sub.-1 to 56.sub.-m. The first DMA processing unit 54 also has a branching controller 52 as a DMA channel for transferring timing data to a second timer 40. When a time specified by the received timing data passes, the second timer 40 sends an activation signal to DMA channel 56.sub.-1 of the second DMA processing unit 56, and the DMA channels 56.sub.-1 to 56.sub.-m are thereafter sequentially activated.
