A method of fabricating a thin film transistor array substrate is provided. First, a first patterned metallic layer, a dielectric layer, an amorphous silicon layer, a second patterned metallic layer and a passivation layer are sequentially formed over a substrate. A patterned photoresist layer is formed over the passivation layer. The patterned photoresist layer at least covers the source/drain (formed out of the first patterned metallic layer) as well as the area beside them. The edges of the patterned photoresist layer have a plurality of thin-out regions. Each thin-out region stretches across part of the edge of one source/drain. Thereafter, using the patterned photoresist layer as an etching mask, an etching operation is carried out until the source/drain and its peripheral amorphous silicon layer under the thin-out regions are exposed to form a plurality of staircase structures. Finally, a plurality of pixel electrodes is formed over the substrate to cover the respective staircase structures and electrically connect to one source/drain electrode.
A method of manufacturing a polysilicon layer is provided. Firstly, a substrate is provided. Next, an amorphous silicon having a first region and a second region is formed on the substrate. After that, the amorphous silicon layer in the first region is completely melted and the amorphous silicon layer in the second region is preheated. The completely melted amorphous silicon layer in the first region is crystallized to form a first polysilicon layer. Next, the preheated amorphous silicon layer in the second region is completely melted. The completely melted amorphous silicon layer in the second region is crystallized to form a second polysilicon layer.
