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Vertical routing structure
   
Document Number
US Patent 6946727
Issued Date
September 20, 2005
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Abstract
A vertical routing structure inside a substrate for connecting a pair of trace lines electrically. The trace lines are positioned on the top and bottom surface of a stack layer. The vertical routing structure includes a conductive rod and two bonding pads. The conductive rod passes through the stack layer such that the top and bottom surface of the conductive rod are also exposed on the top and bottom surface of the stack layer. In addition, a bonding pad is also attached to the top and bottom surface of the conductive rod respectively. The bonding pads are connected to the aforementioned trace lines. The two bonding pads have a transverse sectional area smaller than the transverse sectional area of the conductive rod. Thus, the vertical routing structure is able to reduce surface area needed to accommodate inter-layer connections and increase routing density within the substrate.
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Number of Claims:
6
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Owner
VIA Technologies, Inc. (Taipei Hsien,TW)
Published
September 20, 2005
Application Number
10/723,971
Filed
November 25, 2003
US Classification
257/698   257/700 257/773 257/E23.067
Int'l Classification
H01L   23/48   (20060101)   H01L   23/498   (20060101)  
Examiner
Assistant Examiner
Attorney/Law Firm
Priority Data
Feb 07, 2003 [TW] 92202068 U
USPTO Field of Search
438/698   438/774   438/699   438/708   438/709   438/182   438/276   438/502   438/621   257/698   257/774   257/699   257/708   257/709   257/182   257/276   257/502   257/621   257/700   257/773  
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7446403 - Carrier structure stacking system and method - Owned by Entorian Technologies, LP (Austin, TX)

The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC and the upper shoulder of leads of a lower IC while conductive transits that implement stacking-related intra-stack connections between the constituent ICs are implemented in multi-layer interposers or carrier structures oriented along the leaded sides of the stack, with selected ones of the conductive transits electrically interconnected with other selected ones of the conductive transits.

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Description
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