Deterministic ATPG test coverage is provided in a logic BIST architecture while reducing test application time and test data volume, as compared to deterministic ATPG patterns. The logic BIST architecture can include a PRPG shadow operatively coupled to a PRPG circuit. The PRPG shadow allows re-seeding of the PRPG circuit with zero cycle overhead. Two compressions can be provided. In a first compression, multiple tests for faults are compressed into one pattern. In a second compression, multiple deterministic ATPG patterns can be compressed into one seed. All patterns provided from the PRPG can be controlled by these seeds so that all care bits are properly set, while all other scan cells are set to pseudo-random values from the PRPG. In this manner, the PRPG can rapidly deliver highly pertinent data to the scan chains of the device under test.
A test apparatus including a means for sending a first test pattern to a device under test (DUT), where the first test pattern is a part of a planned sequence of tests, and further including a means for evaluating the test results received from the DUT, and a method of testing are described. The test results may include anomalous data indicative of a defect in the DUT. If so, a second test pattern that is not part of the planned sequence of tests is selected. The second test pattern is selected based on a diagnosis of the anomalous data by the test apparatus.
A system and method enhance observability of IC failures during burn-in tests. Scan automatic test pattern generation and memory built-in self-test patterns are monitored during the burn-in tests to provide a mechanism for observing selective scan chain outputs and memory BIST status outputs.
Testing of on-chip test structures is accomplished by employing a test apparatus that allows test data to be uploaded into selected data latches associated with respective ones of a plurality of test structures. Tests are performed by selectively providing a test data from the data latch to the associated test structure. Test results may be registered into an adjacent data latch for downloading. Multiple test structures may thereby be tested using only limited probing pad access and wafer area.
The present invention is directed to a logic testing architecture with an improved decompression engine that compresses the seeds of a linear test pattern generator in a manner that is independent of the test pattern set.
Programmable logic devices may use shadow memory for gathering diagnostic information while testing memory blocks. Memory block testing may be performed at any clock speed allowed during normal operation in a system such as the highest allowed clock speed. Built in self test circuitry and address and data paths are formed by loading configuration data into a programmable logic device. During write operations on a memory block under test, test data words are written into the memory block. A comparator compares data words read from the memory block to expected data words received from the test pattern generator to produce corresponding comparison data words. The comparison data words are written into the shadow memory. The same addresses are applied to the memory block under test and the shadow memory, so the stored comparison data words form a test results bit map indicative of errors in the memory block.
