An integrated circuit (IC) chip contains a small non-volatile "ID" memory such as an FeRAM array that stores information associated with manufacturing, testing, and performance of the IC chip. The stored information can include but is not limited to a serial number, a wafer ID, a batch ID, a date code, chip history, test data, and performance information. The storing information on the chip eliminates any difficulty in matching the information with the IC chip and provides a flexible permanent record of any information the manufacturer may find useful. The ID memory thus permits tracking and identification of ICs to a degree that was not previously practical. Additionally, a self-test can compare prior test results stored in the ID memory to current self-test results to detect defects or to select operating parameters of the integrated circuit.
A method and networking apparatus for providing fault tolerance to memory are disclosed. The networking apparatus contains a first memory for storing host/port relationships, a second memory for indicating the status of the first memory, and a processor coupled to the memories for manipulating the memories. Furthermore, the claimed invention may also include an optional third memory for serving as a secondary site for storing information regarding host/port relationships.
A method for testing the integrity of a memory with defective sections under a plurality of operating environments includes testing the memory with defective sections under a plurality of operating environments, recording results of each operating environment test, and comparing the results of the tests. If the results of are the same, the memory with defective sections is declared to have integrity. If not, the memory with defective sections is declared to not have integrity.
