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Overlay vernier
   
Document Number
US Patent 6952886
Issued Date
October 11, 2005
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Abstract
The present invention provides a new and improved overlay vernier that can increase the overlay measurement accuracy. The overlay vernier of the present invention comprises an inner square vernier and an outer square vernier. The outer vernier comprises a central square opening and four trapezoid-shaped openings surrounding the central square opening.
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Number of Claims:
5
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Owner
Published
October 11, 2005
Application Number
10/703,590
Filed
November 10, 2003
US Classification
33/645   33/613 414/935
Int'l Classification
G01B   11/00   (20060101)  
Examiner
Assistant Examiner
Attorney/Law Firm
USPTO Field of Search
33/613   33/645   33/533   33/297   33/298   414/935   414/936   414/937   414/938   414/939   414/940   414/941  
Related Patents
7494830 - Method and device for wafer backside alignment overlay accuracy - Owned by Taiwan Semiconductor Manufacturing Company (Hsin-Chu,TW)

A method for wafer backside alignment overlay accuracy includes forming a buried layer on a front-side of a wafer; forming a conductive layer on the buried layer and patterning a first test structure and a second test structure therein; forming an etch stop layer on the conductive layer; etching through the wafer from the backside to perform an alignment process with the first test structure; and determining an overlay accuracy of the alignment process with the second test structure. The first test structure includes an optical vernier and the second test structure includes an electrical testing structure.

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Description
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