A time-error-compensating apparatus and method corrects errors in a real-time clock caused by temperature fluctuations or other external influences. The apparatus includes a frequency counting unit which counts a high-frequency clock signal and a low-frequency clock signal, and a time compensating unit which computes a clock count compensation value based on a comparison of the count values of of the low-frequency and high-frequency clock signals. Correcting time using a high-frequency clock is highly desirable because a clock of this type has proven to be accurate in high external stress conditions. Use of this clock also allows the real-time clock to be implemented as a low-frequency, inexpensive low-frequency clock. The method and apparatus are well suited to correcting time information in the terminals of a mobile communications system, or in any other system or device where time tracking is sought.
Apparatus and methods for estimating the frequency of a sleep or slow clock using a fast clock, such as a temperature compensated crystal oscillator. The disclosed apparatus include an estimator having a first counter that receives sleep clock synchronized pulses issuing each cycle of the sleep clock period, yet are synchronized to a fast clock. The slow clock synchronized pulses are counted up to a predetermined number; whereupon a full count signal is issued. A second counter receives the full count signal and increments each time the full count signal is received. A third counter counts fast clock cycles until the full count signal occurs. Based on the number of counts of the slow and fast clock cycles, the frequency of the slow clock may be determined using only the domain of the fast clock for performing the measurement thereby tying accuracy of the measurement to the accuracy of the fast clock. The disclosed apparatus also include an integrated circuit and a transceiver employing the disclosed estimator. Corresponding methods are also disclosed.
Apparatus and methods for estimating the frequency of a sleep or slow clock by selectively utilizing an estimated sleep clock frequency and an estimated change in the sleep clock frequency. The disclosed apparatus includes a sleep clock frequency estimator to output a fast clock derived sleep clock frequency estimate and a sleep clock change frequency estimator to output an estimate of a change in frequency of the sleep clock. The apparatus further includes a combiner that weights at least one of the fast clock derived sleep clock frequency estimate to obtain a weighted sleep clock frequency estimate and the estimate of the change in frequency of the sleep clock to obtain a weighted estimate of the change in frequency of the sleep clock. The combiner also determines a new estimate of the sleep clock frequency using at least one of the weighted sleep clock frequency estimate and the weighted estimate of the change in frequency of the sleep clock. Complementary methods are also disclosed.
A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates whether the frequency of the one clock signal is faster, slower or substantially equal to the frequency of the other clock signal. Once determined, the status may be stored as a bit pattern within a status register, which is operatively coupled to the clock monitor circuit. This enables the status to be read by detecting a logic state of one or more bits within the status register.
