A memory array comprising nanoscale wires is disclosed. The nanoscale wires are addressed by means of controllable regions axially and/or radially distributed along the nanoscale wires. In a one-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires and microscale wires. In a two-dimensional embodiment, memory locations are defined by crossing points between perpendicular nanoscale wires. In a three-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires located in different vertical layers.
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. provisional Patent Application Ser. No. 60/398,943 filed Jul. 25, 2002 for a "Modulation Doped Molecular-Scale Address Decoding" by Andre' DeHon, Patrick Lincoln, U.S. provisional Patent Application Ser. No. 60/400,394 filed Aug. 1, 2002 for a "Implementation of Computation Note 15: Integration Issues for Modulation Doped Memory" by Andre' DeHon, Patrick Lincoln, U.S. provisional Patent Application Ser. No. 60/415,176 filed Sep. 30, 2002 for "Nanoscale Architectures based on Modulation Doping" by Andre' DeHon, Patrick Lincoln, Charles Lieber, U.S. provisional Patent Application Ser. No. 60/429,010 filed Nov. 25, 2002 for "Stochastic Assembly of Sublithographic Nanoscale Interfaces" by Andre' DeHon, Patrick Lincoln, John E. Savage, U.S. provisional Patent Application Ser. No. 60/441,995 filed Jan. 23, 2003 for "Stochastic Assembly of Sublithographic Nanoscale Interfaces" by Andre' DeHon, Charles Lieber, Patrick Lincoln, U.S. provisional Patent Application Ser. No. 60/465,357, Ser. No. not yet assigned, filed Apr. 25, 2003 for "Sublithographic Nanoscale 3D Architectures" by Andre' DeHon, and U.S. provisional Patent Application Ser. No. 60/467,388, Ser. No. not yet assinged, filed May 2, 2003 for "Computing with Electronic Nanotechnologies" by John E. Savage, Andre' DeHon, Patrick Lincoln, Lee-Ad Gottlieb, Arkady Yerukhimovich, the disclosure of all of which is incorporated herein by reference. Also incorporated by reference is the disclosure of U.S. patent application Ser. No. 10/627,405 filed on the same day of the present application for a "Stochastic Assembly of Sublithographic Nanoscale Interfaces" by John E. Savage, Andre' DeHon, Patrick Lincoln, and Charles Lieber.
A nanoscale or partial nanoscale interface within an electronic device, and a method for producing such interfaces without the need for precise nanoscale alignment of nanoscale elements of a first circuit layer to elements of a second circuit layer, is disclosed. In one embodiment, dimensions of conductive windows fabricated on microelectronic elements are carefully specified, and redundant nanoscale elements are introduced, in order to produce functional nanoscale-to-microscale interfaces despite imprecise nanoscale alignment of nanoscale elements to microscale elements.
An architecture for nanoscale electronics is disclosed. The architecture comprises arrays of crossed nanoscale wires having selectively programmable crosspoints. Nanoscale wires of one array are shared by other arrays, thus providing signal propagation between the arrays. Nanoscale signal restoration elements are also provided, allowing an output of a first array to be used as an input to a second array. Signal restoration occurs without routing of the signal to non-nanoscale wires.
A method includes providing a crossbar array including a programmable material layer, wherein the crossbar array is configured to function as part of a signal processing system and reprogramming at least one impedance value of the programmable material layer formed at crosspoints of the crossbar array to change the signal processing system.
A method including storing two-dimensional binary data in the form of high or low resistance states into a crossbar array with a programmable material layer and transforming the two-dimensional binary data into one-dimensional analog data via the crossbar array.
