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Multiprocessor write-into-cache system incorporating efficient access to a plurality of gatewords
   
Document Number
US Patent 6973539
Issued Date
December 6, 2005
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Abstract
A multiprocessor write-into-cache data processing system includes a feature for preventing hogging of ownership of a first gateword stored in the memory which governs access to a first common code/data set shared by processes running in the processors by imposing first delays on all other processors in the system while, at the same time, mitigating any adverse effect on performance of processors attempting to access a gateword other than the first gateword. This is achieved by starting a second delay in any processor which is seeking ownership of a gateword other than the first gateword and truncating the first delay in all such processors by subtracting the elapsed time indicated by the second delay from the elapsed time indicated by the first delay.
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Number of Claims:
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Published
December 6, 2005
Application Number
10/426,409
Filed
April 30, 2003
US Classification
711/130   711/119 711/121 711/152
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USPTO Field of Search
711/121   711/130   711/152  
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