A magnetic random access memory (MRAM) includes a first memory array having a plurality of first memory cells, wherein each one of the plurality of first memory cells is arranged at an intersection of at least one of a plurality of wordlines, at least one of a plurality of bitlines, and at least one of a plurality of digit lines, a second memory array having a plurality of second memory cells, wherein each one of the plurality of second memory cells is arranged at an intersection of at least one of the plurality of wordlines, at least one of a first bitline and a second bitline, and at least one of the plurality of digit lines, a current providing unit for providing a second current to one of the first bitline and the second bitline in response to a reference voltage, and a sense amplifier for comparing a first current flowing through one of the plurality of bitlines with the second current. A constant current flows to a reference data line without adjusting a level of the reference voltage. Therefore, it is possible to efficiently and accurately sense current of a bitline and determine a logic state of a selected memory cell.
A Resistance based Random Access Memory (ReRAM) can include a current reference circuit including at least three ReRAM reference cells coupled in parallel with one another and configured to provide a reference current to respective ReRAM sense amplifier circuits.
A precision sense amplifier apparatus includes a current source configured to introduce an adjustable reference current through a reference leg; a current mirror configured to mirror the reference current to a data leg, the data leg selectively coupled to a programmable resistance memory element; an active clamping device coupled to the data leg, and configured to clamp a fixed voltage across the memory element, thereby establishing a fixed current sinking capability thereof; and a differential sense amplifier having a first input thereof coupled to the data leg and a second input thereof coupled to the reference leg; wherein an output of the differential sense amplifier assumes a first logic state whenever the reference current is less than the fixed current sinking capability of the memory element, and assumes a second logic state whenever the reference current exceeds the fixed current sinking capability.
A circuit and method for providing an output current that includes biasing an output transistor in accordance with a reference current to conduct the output current and further includes maintaining a voltage across the output transistor. One embodiment includes conducting a reference current through a diode-coupled first field-effect transistor (FET) and biasing a gate of a second FET matched to the diode-coupled first FET by a voltage equal to a gate voltage of the diode-coupled first FET. A current equal to the reference current is conducted through a third FET having a gate coupled to a drain of the second FET, the third FET matched to the second FET.
