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Bidirectional wire I/O model and method for device simulation
   
Document Number
US Patent 6985842
Issued Date
January 10, 2006
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Inventors
Tsyrkina; Yelena M. (South Burlington, VT)
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Abstract
A system and method is provided to accurately model bidirectional wire I/O using hardware description language (HDL). The preferred model and method uses an HDL model that provides two parallel paths between ports of the bidirectional wire I/O. During simulation, the ports are monitored for activity. When an event is detected on either port, the model checks both ports to see if they are different values. If the ports are different values, one of the two parallel paths is enabled and the other disabled. For example, the model enables the path in which the new signal has appeared and thus passes the signal to the other port. The preferred model allows for the use of HDL elements that support full timing annotation. The preferred embodiment also removes the possibility of high impedance transition error that can result from false transitions to a high impedance state.
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Number of Claims:
24
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Published
January 10, 2006
Application Number
09/854,038
Filed
May 11, 2001
US Classification
703/15   703/13 703/14
Int'l Classification
G06F   17/50   (20060101)  
Examiner
Assistant Examiner
USPTO Field of Search
703/15  
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Description
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