Each pixel of a solid state imaging element includes a photodiode, a field effect transistor (FET) having a gate connected to an output of the photodiode, a first feedback circuit connecting the gate and drain of the FET with a first switch inserted in series in a middle thereof, a second feedback circuit connecting the gate and drain of the FET with a second switch and a first capacitor in series in a middle thereof, and a second capacitor connected between a middle of the first capacitor and the second switch and an electric potential. A charge detector includes a capacitor, an amplifier having a negative input connected to the capacitor, a reset switch connected in a feedback circuit connecting an output of the amplifier and the negative input of the amplifier, and at least one circuit connected in parallel with the feedback circuit and having an additional reset switch connecting an output of the amplifier and the negative input of the amplifier and an additional capacitor.
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is a divisional application of U.S. application Ser. No. 09/598,055 filed Jun. 21, 2000 now U.S. Pat. No. 6,781,627 which is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-178388 filed Jun. 24, 1999; and No. 11-354415 filed Dec. 14, 1999, the entire contents of which are incorporated herein by reference.
Priority Data
Jun 24, 1999 [JP] 11-178388 Dec 14, 1999 [JP] 11-354415
