Disclosed is a solid-state imaging device comprising pickup circuit formed by the arrangement of a unit cell in two dimensions, a plurality of reading lines provided in a horizontal direction corresponding to each pixel row in the pickup region to transmit the reading drive signal .phi.READi for driving each reading circuit of the unit cell of respectively corresponding pixel row, a vertical drive selection circuit configured to drive the reading circuit by selectively supplying the reading drive signal to these reading lines, and first row selection circuit and a second row selection circuit configured to control the vertical drive circuit so as to drive reading circuit of each pixel row on the basis of the first pulse and the second pulse .phi.ROREAD and .phi.ESREAD respectively. The solid-state imaging device is capable of controlling a minimum electric charge accumulation time in the photodiode to less than 1H (a horizontal cycle) and is capable of conducting an extremely high-speed shutter operation.
An image sensor comprising a matrix of solid-state light sensor elements each representing a unit pixel, which is capable of reading out sensor signals from respective pixels in a time series by sequentially selecting pixels on a line-by-line basis and sequentially selecting pixels in a selected line, wherein each pixel line is divided into a plurality of blocks with each block composed of the same specified number of pixels and a first scanning means sequentially reads pixel sensor signals on the block-by-block basis starting from the first block and a second scanning means reads pixel sensor signals of the readout block. The image sensor thus constructed can achieve high speed scanning of respective pixels with a minimal increase in power consumption.
A solid-state imaging device, such as a CMOS sensor, includes a unit pixel having a charge generation unit for generating signal charge, a floating diffusion for accumulating the signal charge generated by the charge generation unit, a transfer gate transistor for transferring the signal charge in the charge generation unit to the floating diffusion, a reset transistor for resetting the floating diffusion, and an amplifying transistor for generating a signal in accordance with the signal charge generated by the charge generation unit and outputting the signal to a vertical signal line. The width of a reset pulse for driving the reset transistor is sufficiently decreased to, for example, less than or equal to 1/2, and preferably less than or equal to 1/5 of the response time of a signal that has occurred on the vertical signal line in response to the reset pulse.
