A first comparator makes a comparison between potentials on paired signal lines connected with the secondary winding of a transformer to produce a signal indicating whether data of a first value has been received or not. A second comparator makes a comparison between potentials on the paired signal lines to output a signal indicating whether data of a second value has been received or not. A first detector samples the output signal of the first comparator at regular sampling intervals to produce a signal indicating whether an output signal indicating the reception of data of the first value has been produced from the first comparator. A second detector samples the output signal of the second comparator at the regular sampling intervals to produce a signal indicating whether an output signal indicating the reception of data of the second value has been produced from the second comparator.
An encoding technique is disclosed for mitigating against the effects of Intersymbol Interference (ISI) and DC creep by forcing data transitions at least every two data bits. Two consecutive bits of data in the original non-return-to-zero (NRZ) data stream are grouped and are converted by an encoding circuit into two new consecutive data bits of the same duration as the original bits. The new encoded bits in each group will necessarily transition between two of three possible data states, and specifically will transition between `-1` and `0` logic states, or `+1` and `0` logic states. Pursuant to this encoding scheme, no more than two consecutive encoded bits will ever be of the same logic state, which prevents any particular data state from predominating and causing DC creep.
