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Method and apparatus for reducing power consumption in a memory bus interface by selectively disabling and enabling sense amplifiers
   
Document Number
US Patent 7000065
Issued Date
February 14, 2006
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Abstract
A method and apparatus for selectively disabling sense amplifiers to reduce power consumption in a memory bus interface are disclosed. The method includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence or end of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus. According to some embodiments, the disabling of the amplification may be synchronized to an edge of a delayed data strobe signal. In some embodiments, signals associated with a double data rate ("DDR") synchronous dynamic random access memory ("SDRAM") device may be communicated over the memory bus.
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Number of Claims:
10
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Owner
Intel Corporation (Santa Clara, CA)
Published
February 14, 2006
Application Number
10/038,960
Filed
January 2, 2002
US Classification
711/105   365/205 365/207 365/208 365/227 365/233 711/167 713/320 713/324
Int'l Classification
G06F   12/00   (20060101)  
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USPTO Field of Search
711/105   711/167   713/324   713/320   365/205   365/207   365/208   365/227   365/233  
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