A content addressable memory (CAM) device can include a plurality of CAM super-blocks each comprising a plurality of sub-blocks. Each sub-block can include a plurality of CAM entries that generate match results in response to a key value. For each sub-block there can be storage for a programmable local priority value that establishes priority of match results of the sub-block with respect to match results of the other sub-blocks of the same CAM super-block. In addition, for each sub-block there can be a programmable global priority value, different from the programmable local priority value, that establishes priority of match indications of the sub-block with respect to match results of sub-blocks of the plurality of CAM super-blocks.

A priority encoder circuit can include a number of sectional encoder circuits that each encode "m" inputs signals into sets of "P" encoder outputs, where m>p. Each sectional encoder circuit can also output a group indication signal representing the activation of any of the received m encoding input signals. Priority encoder logic can prioritized the group indication signals. A memory can include a different storage location accessed by each prioritized group indication signal.

Content addressable memory (CAM) in which search results such as an address code and an array match signal can be obtained for multiple search widths. The CAM includes a CAM array that can provide match signals and suppress signals for memory locations. Match combining circuitry combines the match signals for memory locations to obtain combined match signals; the combination depends on an indicated search width, which can be one of a set of multiples of the memory location width. A priority encoder provides a priority signal indicating a combined match signal that has priority and is asserted; the priority encoder can therefore be smaller than would be necessary to prioritize all the match signals. An address encoder obtains most significant bits of an address code in response to the priority signal. Select circuitry responds to the priority signal by selecting match signals and suppress signals for the combined match signal with priority. The selected match signals are used to obtain least significant bits (LSBs) of the address code in accordance with the search width. The LSBs, selected suppress signals, and a PE match signal from the priority encoder are used to obtain an array match signal.

A sense amplifier circuit can be coupled to a match line for receiving a match line voltage and to a low potential line for receiving a low potential voltage from a memory array. The sense amplifier circuit can include a charging circuit coupled between a power supply voltage and the match line voltage that comprises no p-channel transistors. A discharging circuit can be coupled between the low potential voltage and a ground supply voltage. An n-channel sensing device can coupled to detect a potential difference between the match line voltage and the low potential voltage.

A content addressable memory (CAM) device (200) can include a control block (202) having a dummy control circuit (216). A dummy control circuit (216) can initiate dummy searches (or other operations) prior to and/or during actual searches to reduce overall supply current transients. Methods for initiating dummy searches are also disclosed.