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Method and coding apparatus using low density parity check codes for data storage or data transmission
   
Document Number
US Patent 7000168
Issued Date
February 14, 2006
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Abstract
A method of generating low density parity check codes for encoding data includes constructing a parity check matrix H from balanced incomplete block design (BIBD) in which a plurality B-sets which define the matrix have no more than one intersection point. The parity bits are then generated as a function of the constructed parity check matrix H.
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Number of Claims:
19
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Owner
Seagate Technology LLC (Scotts Valley, CA)
Published
February 14, 2006
Application Number
10/093,926
Filed
March 8, 2002
US Classification
714/755   714/800 714/801 714/804
Int'l Classification
H03M   13/00   (20060101)  
Examiner
Attorney/Law Firm
Parent Case
CROSS-REFERENCE TO RELATED APPLICATION This application claims priority from U.S. Provisional Application No. 60/296,223, filed Jun. 6, 2001, and entitled "METHOD AND CODING USING LOW DENSITY PARITY CHECK CODES FOR DATA STORAGE OR DATA TRANSMISSION", AND U.S. Provisional Application No. 60/314,987, filed Aug. 24, 2001, and entitled "A METHOD AND CODING MEANS USING ANTI-PASCH LDPC CODES".
USPTO Field of Search
714/755   714/704   714/786   714/800   714/804   714/801  
Related Patents
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A low density parity check (LDPC) code generating method and apparatus are provided. A parity check matrix with (N-K) rows for check nodes and N columns for variable nodes are formed to encode an information sequence of length K to a codeword of length N. The parity check matrix is divided into an information part matrix with K columns and a parity part matrix with (N-k) columns. The parity part is divided into P.times.P subblocks. P is a divisor of (N-K). First and second diagonals are defined in the parity part matrix and the second diagonal is a shift of the first diagonal by f subblocks. Shifted identity matrices are placed on the first and second diagonals and zero matrices are filled elsewhere. An odd number of delta matrices each having only one element of 1 are placed in one subblock column of the parity part matrix. The parity check matrix is stored.

7483496 - Method and system for providing long and short block length low density parity check (LDPC) codes - Owned by The DIRECTV Group, Inc. (El Segundo, CA)

An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For 1/3 rate, the relevant parameters are as follows: q=120, n.sub.ldpc=64,800, k.sub.ldpc=n.sub.BCH=21600, k.sub.BCH=21408 (12 bit error correcting BCH). For 1/4 rate, the LDPC code has the following relevant parameters: q=135, n.sub.ldpc=64,800, k.sub.ldpc=n.sub.BCH=16200, k.sub.BCH=16008 (12 bit error correcting BCH). For 2/5 rate, the following parameters exist: q=108, n.sub.ldpc=64800, k.sub.ldpc=n.sub.BCH=25920, k.sub.BCH=25728 (12 bit error correcting BCH). The above approach has particular application in digital video broadcast services over satellite.

7376883 - Method and system for providing long and short block length low density parity check (LDPC) codes - Owned by The DIRECTV Group, Inc. (El Segundo, CA)

An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For 1/3 rate, the relevant parameters are as follows: q=120, n.sub.ldpc=64,800, k.sub.ldpc=n.sub.BCH=21600, k.sub.BCH=21408 (12 bit error correcting BCH). For 1/4 rate, the LDPC code has the following relevant parameters: q=135, n.sub.ldpc=64,800, k.sub.ldpc=n.sub.BCH=16200, k.sub.BCH=16008 (12 bit error correcting BCH). For rate, the following parameters exist: q=108, n.sub.ldpc=64800, k.sub.ldpc=n.sub.BCH=25920, k.sub.BCH=25728 (12 bit error correcting BCH). The above approach has particular application in digital video broadcast services over satellite.

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An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a short LDPC code by shortening longer mother codes. The short LDPC code has an outer Bose Chaudhuri Hocquenghem (BCH) code. According to another aspect, for an LDPC code with code rate of 3/5 utilizing 8-PSK (Phase Shift Keying) modulation, an interleaver provides for interleaving bits of the output LDPC code by serially writing data associated with the LDPC code column-wise into a table and reading the data row-wise from right to left. The above approach has particular application in digital video broadcast services over satellite.

7506238 - Simplified LDPC encoding for digital communications - Owned by Texas Instruments Incorporated (Dallas, TX)

Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix arrangement of the LDPC parity check matrix in which the parity portion of the parity check matrix is arranged as a macro matrix in which all block columns but one define a recursion path. The parity check matrix is factored so that the last block column of the parity portion includes an invertible cyclic matrix as its entry in a selected block row, with all other parity portion columns in that selected block row being zero-valued, thus permitting solution of the parity bits for that block column from the information portion of the parity check matrix and the information word to be encoded. Solution of the other parity bits can then be readily performed, from the original (non-factored) parity portion of the parity check matrix, following the recursion path.

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Description
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