Provided are methods and apparatuses for decoding input data by using a single decoder for decoding a first set of symbols and then, after those decoded symbols have been interleaved, using the same decoder for decoding the decoded and interleaved first set of symbols together with a second set of symbols. Also provided are methods and apparatuses for decoding input data by using multiple read/write means for controlling the storage and reading of data so as to interleave and/or de-interleave data simultaneously with data buffering.
A device for processing data to be interleaved and stored in target memories includes N interleaving buffers, N producers, and N cells. Each cell includes a register bank of size W, and a delay circuit. The variable M defines a maximum number of concurrent write operations supported per time step W, and defines a maximum buffer size. These parameters are chosen to reflect a standard case. At any time step, each of the N interleaving buffers receives m log-likelihood ratio (LLR) inputs and writes up to M of these into the register banks. When m is larger than M, m-M producers are delayed by the delay circuit. When a buffer overflow occurs (more than W LLRs values), m producers are delayed by the delay circuit. One LLR value is fetched from the register bank and is written in an SRAM interleaving memory.
