A semiconductor memory device comprises a memory cell array comprising memory cells of a first type. The memory cell array performs write and read operations in response to signals designed for the operation of a memory cell array comprising memory cells of a type other than the first type.

After a refresh operation, a word control circuit holds the selection state of a word line selection signal line selected in each memory block corresponding to a refresh address. Further, in response to an access request, the word control circuit unselects only a word line selection signal line of a memory block selected by an external address corresponding to this access request. In each memory block, the word line selection signal line once selected is not unselected until the access request is received, so that the frequency of unselection and selection of the word line selection signal lines can be lowered. Consequently, a charge/discharge current of the word line selection signal lines can be reduced, which can reduce current consumption of a semiconductor memory.

A processor boot-up controller includes: a volatile memory connected to a nonvolatile memory; a selector, which transfers boot-up codes to the volatile memory from the nonvolatile memory; a controller for the nonvolatile memory configured from a boot-up control sequencer, which transmits CPU read-in data to the CPU and brings the CPU into a wait state until boot-up code transfer completes; and an error detection and correction unit connected to the external CPU and the nonvolatile memory. The processor boot-up controls the CPU by reading data from the nonvolatile memory. The processor enables the CPU to access a SRAM in the shortest time in sync with the SRAM's ready timing, resulting in a reduction of average system boot-up time. An information processing system can use the controller for example for a nonvolatile memory, a microprocessor boot-up controller, and multi-valued nonvolatile memory.