A system and method of calibrating a digital-to-analog converter (DAC) such as a resistor string DAC that reduces costs by making more efficient use of integrated circuit chip area, without requiring analog calibration circuits. The DAC calibration system includes a main DAC to be calibrated, a memory, and calibration logic circuitry for performing arithmetical operations. The memory stores a predetermined number of digital code values in respective memory locations, which are indexed by corresponding voltage values. The digital code values represent DAC input code values which, when applied to the main DAC, would generate the corresponding index voltage values as DAC output voltage levels. The stored DAC input code values and the corresponding DAC output voltage levels, which are determined using an external tester, define piecewise linear (PWL) breakpoint code values of a PWL approximation of the DAC transfer function.
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority of U.S. Provisional Patent Application No. 60/534,733 filed Jan. 7, 2004 entitled ALL-DIGITAL CALIBRATION OF STRING DAC LINEARITY USING AREA EFFICIENT PWL APPROXIMATION: ELIMINATING HARDWARE SEARCH AND DIGITAL DIVISION.
