A reconfigurable ADC includes a plurality of reconfigurable blocks for allowing the ADC to provide a plurality of architectures. In one embodiment, the ADC can be configured to operate in a pipeline mode and a sigma-delta mode. This arrangement provides an ADC having a relatively large range of bandwidth and resolution.
CROSS-REFERENCE TO RELATED APPLICATIONS
This Application is a continuation of U.S. patent application Ser. No. 10/755,655, now U.S. Pat. No. 6,864,822, filed on Jan. 12, 2004, which is a continuation of U.S. patent application Ser. No. 09/735,219 filed on Dec. 12, 2000, now U.S. Pat. No. 6,686,860, both of which are incorporated herein by reference in their entirety.
In general, in one aspect, the disclosure describes a hybrid analog-to-digital converter. The hybrid converter comprises a successive approximation analog-to-digital converter for receiving an analog input signal and generating at least one bit of a digital output signal and a cyclic analog-to-digital converter coupled to the analog input signal and the successive approximation analog-to-digital converter for generating at least one additional bit of the digital output signal.
Circuits and methods to achieve a voltage-to-current converter having low noise and a high linearity are disclosed. In a preferred embodiment the converter has been used as a Gm integrator. The core of the invention is an operational transconductance amplifier (OTA) having additional DC current sources allowing a common mode voltage shift. The feedback currents and output currents are decoupled by means of current mirrors. The feedback currents are higher than the output currents thus allowing lower integration resistor size. A common mode decoupling of input and output has been achieved by current mirrors.
One embodiment of the present invention includes a pipelined analog-to-digital converter (ADC) comprising a plurality of pipeline stages. At least one of the plurality of pipeline stages comprises a feedback transistor-follower combination interconnected between a positive source voltage and a summation node and configured to set a voltage of the summation node approximately equal to a sample-and-hold voltage associated with a preceding one of the plurality of pipeline stages. The at least one of the plurality of pipeline stages also comprises a current mirror coupled to the feedback transistor-follower combination configured to provide a first current that is approximately equal to a second current that is associated with the feedback transistor-follower combination. The at least one of the plurality of pipeline stages further comprises an output resistor configured to set an output voltage of the respective at least one of the plurality of pipeline stages based on the first current.
