A method for providing dynamic element matching of capacitors in a pipelined analog to digital converter (ADC). Instead of randomizing the output of a flash ADC before providing the output of the ADC to the capacitor array, the threshold voltages from a reference ladder are randomized. This eliminates multiple, series connected switches of a randomizer between the output of a comparator bank and the capacitor array, and may be done during the time the output of the comparator bank of the flash ADC is latched, thereby not negatively impacting the speed of operation of the pipelined ADC.
Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide pipelined analog to digital converters. Such converters include a sub-converter and a residue amplifier. The sub-converter receives an analog input, and provides a digital representation of the analog input including a number of bits. A gain of the residue amplifier is controlled by selectably setting a group of switches. Each of the number of bits output from the sub-converter electrically controls a respective one of the switches.
Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide methods for performing analog to digital conversions that include providing an analog to digital converter with a residue amplifier that is associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors. The methods further include performing a first sample of an analog input voltage by charging the first set of input capacitors from the analog voltage input during a first period; amplifying the first sample during a second period; performing a second sample of the analog input voltage by charging the second set of input capacitors from the analog voltage input during a third period; and amplifying the second sample during a fourth period.
Each stage of a pipeline ADC includes an analog delay cell, a sub-stage ADC, and a multiplying digital-to-analog converter (MDAC). The MDAC includes a sample-and-hold amplifier (SHA) circuit, a summer, a gain stage, and a DAC. The MDAC is arranged in cooperation with the analog delay cell such that the effects of a long comparator decision time under high-speed conditions are minimized. The first SHA, half clock cycle delay cell with unity gain transfer function, samples the input signal during the first clock period, followed by a strobe of the sub-ADC. Substantially half of the clock period can be utilized for the comparison time of the sub-ADC using the described methods. Since decoding is completed before MDAC sampling the first SHA output so that the complete half clock cycle can be arranged for amplifier settling in order to achieve the maximum operating speed with a given amplifier bandwidth.
An analog-to-digital converter (ADC) includes a multiplying digital-to-analog converter (MDAC) having a plurality of capacitors and a plurality of capacitor positions. The ADC generates a random number for a conversion cycle. The ADC configures each capacitor of the plurality of capacitors in a corresponding capacitor position of the plurality of capacitor positions based on the random number for the conversion cycle. The ADC converts, for the conversion cycle, a voltage of an analog signal to a digital value based on the capacitor configurations.
