In an IC card 30 is sealed an IC chip 70 provided with an exposure sensor 84. When exposure sensor 84 detects that IC card 30 has been opened, exposure sensor 84 outputs an exposure detection signal to a CPU 76. In response to the exposure detection signal, CPU 76 provides a predetermined operation, such as erasure of data in a non-volatile memory 78. As such, the data in non-volatile memory 78 cannot be obtained if IC card 30 is improperly opened to check the data in non-volatile memory 78. Thus the IC card can obtain an enhanced data security.
CROSS-REFERENCES TO PRIORITY APPLICATIONS
This is a continuation application which claims the benefit of pending U.S. patent application Ser. No. 09/423,293, now Pat. No. 6,802,008, filed Nov. 15, 1999, which in turn is a National Stage application of PCT/JP98/01023, filed Mar. 11, 1998. The disclosure of the prior applications is hereby incorporated herein in their entirety by reference.
A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair of adjacent inner leads for power supply terminal and ground terminal are extended inwardly; a chip capacitor mounting pad which is provided at inner ends of the extended inner leads; and a chip capacitor which is mounted on the chip capacitor mounting pad so that a decoupling capacitor is provided.
A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair of adjacent inner leads for power supply terminal and ground terminal are extended inwardly; a chip capacitor mounting pad which is provided at inner ends of the extended inner leads; and a chip capacitor which is mounted on the chip capacitor mounting pad so that a decoupling capacitor is provided.
