A system and methodology for testing memory in an integrated circuit implementing BIST testing to calculate row and column redundancy and enable replacement of a defective row or column of memory cells. The system comprises circuitry for detecting a first single memory cell failure in a row; and, recording the I/O value of the first Single Cell Fail (SCF). A circuit is provided for detecting whether more than one single cell failure has occurred for a tested row, and, in response to detecting a second SCF, comparing recorded I/O value of the subsequent tested row, with the I/O value associated with the first failed memory cell. Upon detection of defective bits, the defective column and row of memory having corresponding defective bits set is replaced.
On chip diagnosis method and on chip diagnosis block with mixed redundancy (IO redundancy and word-register redundancy) is provided. During a BIST (Built-In Self Test), information needed to apply redundancy resources is stored inside two arrays (fill_array, shift_array) on chip. A final diagnosis may apply redundancy resources based on this stored information. The first array (fill_array) is used to keep a minimum error mapping and the second array (shift_array) is used to control the fill of the first array.
