Connection circuitry provides for TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core leads or terminals. This arrangement provides for the merged TAP and scan test port interfaces to be selected individually or in groups. Internal Tap Lock circuitry uses only the existing 1149.1 interface signals to produce a Lock Out signal to enable and disable a TMS/CS signal to the TAP circuitry.
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority under priority under 35 USC 119(e)(1) of provisional application Ser. No. 60/212,417, filed Jun. 19, 2000 and provisional application Ser. No. 60/200,418 filed Apr. 28, 2000.
An electronic circuit, including; a logic circuit having a plurality of logic cells; storage cells able to form a shift register, able to be connected to the logic cells; a connecting control module having an input for the reception of an identification key, the module connecting the storage cells so as to form a test shift register when the receive input receives a valid identification key, and the module connecting the storage cells so as to form randomly a diversion circuit when the input does not receive a valid identification key. The invention allows the electronic circuit to be protected against fraudulent access in read or write mode. The invention also relates to a smart card including this electronic circuit.
A printed circuit board (PCB) may be used in a first mode where boundary scan techniques are used to externally program and/or test devices on the PCB, or a second mode where an internal source programs devices using boundary scan techniques. In one implementation, there is also additional flexibility to include or skip devices in a boundary scan chain and to accommodate non-scan related functions for pins used for scanning. These various modes of operation may be selected by activating and deactivating buffers.
