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Active area bonding compatible high current structures
   
Document Number
US Patent 7005369
Issued Date
February 28, 2006
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Abstract
An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.
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Number of Claims:
44
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Owner
Intersil American Inc. (Milpitas, CA)
Published
February 28, 2006
Application Number
10/698,184
Filed
October 31, 2003
US Classification
438/614   257/E23.02 438/618 438/622 438/624 438/625 438/652
Int'l Classification
H01L   21/44   (20060101)  
Examiner
Parent Case
This application claims the benefit under 35 U.S.C. .sctn.119(e) of U.S. Provisional Application Ser. No. 60/496,881, filed Aug. 21, 2003, and U.S. Provisional Application Ser. No. 60/507,539, filed Sep. 30, 2003, which are incorporated herein by reference.
USPTO Field of Search
438/612   438/614   438/618   438/622   438/624   438/625   438/642   438/652  
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