A digital potentiometer is disclosed that includes first, second, and third signal terminals. A chain of series-connected impedance elements with multiple tap points is connected between the first and second signal terminals. A plurality of first switching devices are each connected to a respective one of the multiple tap points and to an internal wiper node. A configurable output stage is connected between the internal wiper node and the third signal terminal. The configurable output stage includes a buffer and a second switching device. The second switching device is operable to bypass the buffer. A switching circuit controls switching of the first switching devices. The switching circuit includes a Gray-code counter, a Gray-code decoder, and a make-before-break circuit that controls the timing of the switching of the wiper switches.
RELATED APPLICATION
This application is a continuation of U.S. patent application Ser. No. 10/081,499, entitled "Buffered Configurable Nonvolatile Programmable Digital Potentiometer," which was filed on Feb. 20, 2002, issued as U.S. Pat. No. 6,771,053 on Aug. 3, 2004, and is incorporated herein by reference in its entirety.
