Devices for performing analog-to-digital conversion with reduced noise. In one implementation, an analog-to-digital converter includes at least one internal digital-to-analog converter (DAC) that comprises a plurality of analog components and converts an intermediate digital signal into an associated intermediate analog signal, a dynamic element matching (DEM) circuit coupled to the DAC to permute configurations of the analog components within the DAC, a noise cancellation circuit and a digital subtractor block. The noise cancellation circuit is coupled to receive a first digital sequence comprising a component of a digitized representation of an analog output of the DAC, and a second digital sequence representing a state of the DEM circuitry. The noise cancellation circuit is operable to combine the first and the second digital sequences so as to estimate a digital representation of a DAC noise caused by error sequence introduced mismatches among the analog components within the DAC. The digital subtractor block is coupled to the noise cancellation circuit and operable to use the estimated digital representation of the DAC noise to reduce the DAC noise.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation (and claims the benefit of priority under 35 USC 120) of U.S. patent application Ser. No. 09/792,751 filed Feb. 22, 2001, now U.S. Ser. No. 6,734,818; which claims priority to U.S. Provisional Application No. 60/184,205, filed Feb. 22, 2000. The disclosures of the prior applications are considered part of (and are incorporated by reference in) the disclosure of this application.
A sigma-delta modulator is provided with a feedback digital-to-analog converter having less resolution than the quantizer, while providing a reduced length output word, requiring minimal additional internal processing, and shaping of the truncation error by an effective noise transfer function greater than the order of the host sigma-delta modulator.
The most hardware efficient way to implement an N-stage pipeline ADC is to use (G+1)-level ADC-DAC for its first (N-1) stages and use (2G-1)-level ADC for the last stage, where G is the inter-stage gain. For the fist (N-1) stages using (G+1)-level ADC-DAC, the (G+1) levels are uniformly distributed between -(G-1)/G and (G-1)/G; inclusively. The spacing between two adjacent levels is 2(G-1)/G.sup.2. For the last stage using (2G-1)-level ADC, the (2G-1)-levels are uniformly distributed between -(G-1)/G and (G-1)/G, inclusively. The spacing between two adjacent levels is 1/G.
A centered-pulse consecutive edge modulation (CEM) method and apparatus provides a pulse output that advantageously exploits the full edge update rate of the CEM while providing substantially centered pulses. The method and apparatus also operate without substantial delay in the input control path. The apparatus includes a delta-sigma noise shaping modulator followed by a CEM that receives an output of the delta-sigma modulator quantizer. A non-linear correction signal is applied with polarity alternating at each edge and is applied to the quantizer input or is designed into the quantizer transfer function. The non-linear correction signal compensates for the noise-shaping modulator output such that the expected rising edge and falling edge widths of the CEM output pulses are substantially equal with respect to a DC input to the delta-sigma modulator.
A delta-sigma modulator circuit with limiter and method provide extended dynamic range in noise-shaped pulse generators. A limiting circuit is provided to adjust the output of the quantizer of the delta-sigma modulator according to a given range of values. The range is adjusted in conformity with a stored previous value of the output of the limiter. The circuit permits adjustment of pulse widths in a consecutive-edge modulator (CEM) to correct conditions where a minimum high-state or low-state pulse width would be violated by the commanded output value of the quantizer. The adjusting circuit delays the rising edge of the next pulse if the minimum low state pulse width would not be met and/or extends the falling edge portion of the next pulse if the minimum high-state pulse width would not be met.
The present invention is directed to a diagnostic compiler for use with a pipeline analog-to-digital converter (ADC) having code sequences corresponding to stages thereof. In one embodiment, the diagnostic compiler includes a transition locator configured to determine transition locations for the code sequences. The diagnostic compiler also includes a characteristics indicator coupled to the transition locator and configured to provide at least one characteristic of the ADC based on the transition locations.
