A method of manufacturing a semiconductor device is provided. The method includes providing a device isolation region for defining a device region on a mono-crystalline semiconductor layer of an SOI substrate formed with a mono-crystalline semiconductor layer through an embedded insulation payer on a semiconductor substrate of a first conductivity type. An opening is formed penetrating the device isolation region and the embedded insulation layer and reaching the semiconductor substrate. A polysilicon is deposited on the SOI substrate and within the opening and providing a gate electrode and a substrate electrode of the MIS type field-effect transistor by executing the patterning thereon; and implanting impurities into the gate electrode and the substrate electrode.
CROSS REFERENCE TO RELATED APPLICATIONS
This Application is a divisional of and claims the benefit of the earlier filing date of U.S. patent application Ser. No. 09/963,426, filed Sep. 27, 2001 now U.S. Pat. No. 6,566,713, which was also filed in Japan as Application No. 2000-294966 on Sep. 27, 2000.
