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Systems and methods for holdover circuits in phase locked loops
   
Document Number
US Patent 7010076
Issued Date
March 7, 2006
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Abstract
Improved phase locked loops are described which handle momentary breaks in an input communication channel. The phase locked loops provide the capability to "hold" the output clock in a communication system at or very near the last output frequency before the loss of input data. Such phase locked loops include a differential phase detector, an electronic selector circuit, and an operational amplifier based loop filter circuit. The electronic selector circuit provides the differential output of the phase detector at a pair of inputs to the operational amplifier. A voltage controlled oscillator is coupled to an output of the operational amplifier and provides an output frequency for the phased locked loop circuit. The electronic selector circuit is operable to control the input to the operational amplifier to hold an output frequency of the voltage controlled oscillator at a substantially constant frequency.
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Number of Claims:
31
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Owner
ADC Telecommunications, Inc. (Eden Prairie, MN)
Published
March 7, 2006
Application Number
09/432,022
Filed
October 29, 1999
US Classification
375/376  
Int'l Classification
H03D   3/24   (20060101)  
Assistant Examiner
USPTO Field of Search
375/316   375/327   375/373   375/374   375/375   375/376   375/354   375/371   360/55   360/60   327/141   327/146   327/154   327/155   327/156  
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