A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register (34), test port (38) and output control circuits (42, 46) controlled by an event qualifying module (EQM) (32). In response to a matching condition the EQM (32) may perform a variety of tests on incoming data while the integrated circuits (10, 12) continue to operate at speed. A plurality of digital bus monitors (20, 22) may be cascaded for observation and test of variable width data buses and variable width signature analysis.
This application is a divisional of application Ser. No. 10/690,325, filed Oct. 21, 2003, now pending; which was a divisional of application Ser. No. 10/649,274, filed Aug. 27, 2003 now U.S. Pat. No. 6,959,408; which was a divisional of application Ser. No. 09/597,472, filed Jun. 20, 2000, now abandoned; which was a divisional of application Ser. No. 09/265,028, filed Mar. 9, 1999, now U.S. Pat. No. 6,131,171, issued Oct. 10, 2000; which was a divisional of application Ser. No. 08/929,389, filed Sep. 15, 1997, now U.S. Pat. No. 5,905,738, issued May 18, 1999; which was a continuation of application Ser. No. 08/350,933, filed Dec. 7, 1994, now abandoned; which was a continuation of application Ser. No. 07/892,392, filed May 28, 1992, now abandoned; which was a continuation of application Ser. No. 07/708,099, filed May 24, 1991, now abandoned; which was a continuation of application Ser. No. 07/374,896, filed Jun. 30, 1989, now abandoned.
