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Method and apparatus for performing bit-aligned permute
   
Document Number
US Patent 7014122
Issued Date
March 21, 2006
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Abstract
A method and apparatus for performing bit-aligned permute are disclosed. A select register, a pair of data registers and a target register are provided. The entries of the select register is preloaded with a set of bit indices. Each of the bit indices points to a desired bit location within the data registers. The byte information stored in the data registers are then copied to the target register according to the bit indices within the select register.
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Number of Claims:
6
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Published
March 21, 2006
Application Number
10/745,730
Filed
December 24, 2003
US Classification
235/494   235/487
Int'l Classification
G06K   19/06   (20060101)  
Examiner
USPTO Field of Search
712/228   712/32   395/375   395/80   235/494   235/487   235/380   235/375  
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