A memory capable of suppressing disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, and applies prescribed reverse voltages to at least non-selected first storage means connected to a non-selected word line substantially identical times respectively or substantially applies no voltage through a read operation and a rewrite operation.
A device and method of reading a ferroelectric memory, including providing a ferroelectric memory including a ferroelectric memory cell, a charge integrator, and a bit line connecting the ferroelectric memory cell and the charge integrator. Pulses are applied to the ferroelectric memory cell, where each of the pulses are of a value lower than that which will destroy data stored in the memory cell. Output voltage values from the ferroelectric memory cell are accumulated by the charge integrator in response to each pulse. The output of the charge integrator may be read to determine whether the datum value stored in the memory cell is a logic high or low value. In one embodiment, the output of the charge integrator is read at a predetermined time after starting the pulses.
A memory capable of inhibiting a non-selected cell from disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, for applying voltages of opposite directions to the first storage means of a non-selected memory cell by the same number of times or substantially applying no voltages throughout a read operation and a rewrite operation while varying a rewriting method with a case of reading first data by the read operation and with a case of reading second data by the read operation.
