In a JTAG test and debug environment, the parameters that are accessed by command include a delay parameter. The delay parameter prevents the subsequent command from being executed until both the original command has been executed and the clock cycles indicated by the delay parameter have been completed. Because the time delay is included as a parameter identified by the command, the delay parameter can be programmed.

JTAG test equipment arranged to establish an asynchronous data transmission connection with a JTAG-compatible device under test for the transmission of test data between test access ports (TAP) in the test equipment and device under test. The test data is synchronized at reception before the test access ports (TAP). The test equipment includes a computer program for adapting a test data sequence arriving in the format defined by the test access port for transmission on an asynchronous transmission path, and a transceiver (TR1) for adapting the test data sequence and transmitting it through the asynchronous data transmission connection to the device under test.

The inventive interface connects a client system with the server computer. The server computer includes the JTAG scan program, and can issue scan tests to the desired device under test. Thus, the user can remotely operate the JTAG tool, and can use the unix shell or scripting language of their client system, to issue scan commands. The interface converts commands from the client system into commands that the JTAG application can recognize. The interface converts the responses from the device under test into a format that can be delivered to the client computer. The interface uses TCP/IP protocol for communications between server and client processes.

A method for debugging a target processor is provided that includes storing a plurality of data values to be sent to the target processor in a first-in first-out (FIFO) buffer unit, saving a copy of an address in a read address counter of the FIFO buffer unit, wherein the address is that of an initial data value of a sequential portion of the plurality of data values, performing a transfer operation to send the sequential portion to the target processor, wherein the read address counter is incremented as each data value is sent. The method also includes resetting the read address counter with the copy of the address if the transfer operation fails and performing the transfer operation again.

An integrated device (e.g., an integrated PCI bridge device), having configuration registers for storing configuration values, device logic for generating internal state values based on the configuration values, and a JTAG interface configured for receiving a serial input stream and outputting a serial output stream, further includes write logic and debug read logic. The write logic is configured for writing selected portions of the serial input stream into respective selected ones of the configuration registers, based on a detected input indicating a JTAG-based override. The debug read logic is configured, in response to a detected debug mode, for outputting selected internal state values for the serial output stream, based on selection values from the serial input stream and having been stored in a prescribed at least one of the selected configuration registers.