NMOS composite device Vds bootstrappers that mitigate the effects of decreased power supply rejection and increased channel length modulation in minimum or short channel length devices. The NMOS composite devices have a native or at least a low threshold device over a short channel device, with the gate of the native or low threshold device being controlled responsive to the input or output of the short channel device to clamp the drain--source voltage of the short channel device while holding the short channel device in saturation. In one embodiment, a native device is used, with the gate or the native device being connected to the gate of the short channel device. Other embodiments, including embodiments in the form of source followers having enhanced linearity are disclosed.
A method and apparatus are provided for summing DC voltages, which employ at least one native transistor device to add a first DC input voltage to a second DC input voltage to produce a sum output.
A method is provided for improving the performance of a circuit containing a three-terminal device. In the operation of a circuit containing three-terminal device 10, the influence of the Early effect pertaining to the three-terminal device of a FET is reduced. In order to reduce the influence, control unit 30 is set for reducing the Early effect component caused by a three-terminal device. As a result, by controlling the potential of the second terminal (such as drain) of the device as a response to a first signal pertaining to the input signal received by the first terminal (such as gate) of the device, it is possible for the potential difference between the second terminal (drain) and the third terminal (such as source) of the device to be essentially constant.
